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參數(shù)資料
| 型號： | MB15F73UL |
| 廠商： | Fujitsu Limited |
| 英文描述： | ASSP Dual Serial Input PLL Frequency Synthesizer |
| 中文描述： | ASSP的雙串行輸入鎖相環(huán)頻率合成器 |
| 文件頁數(shù)： | 9/18頁 |
| 文件大小： | 155K |
| 代理商： | MB15F73UL |
9
MB15F73UL
Dec. 2000
Edition 2.0
Table2. Binary 14-bit Programmable Reference Counter Data Setting
Note:
Divide ratio less than 3 is prohibited.
Table.3 LD/fout output Selectable Bit Setting
Divide
ratio
(R)
R
14
R
13
R
12
R
11
R
10
R
9
R
8
R
7
R
6
R
5
R
4
R
3
R
2
R
1
3
0
0
0
0
0
0
0
0
0
0
0
0
1
1
4
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
0
1
0
1
16383
LD/fout pin state
LDS
T1
T2
LD output
0
0
0
0
1
0
0
1
1
fout
output
fr
IF
1
0
0
fr
RF
1
1
0
fp
IF
1
0
1
fp
RF
1
1
1
Programmable Counter
C
N
1
1
2
L
D
S
3
F
C
4
A
1
5
A
2
6
A
3
7
A
4
8
A
5
9
A
6
10
A
7
11
N
1
12
N
2
13
N
3
14
N
4
15
N
5
16
N
6
17
LSB
MSB
Data Flow
C
N
2
S
W
18
CN1, 2
N1 to N11
A1 to A7
SW
IF/RF
: Control bit
: Divide ratio setting bits for the programmable counter (3 to 2,047)
: Divide ratio setting bits for the swallow counter (0 to 127)
: Divide ratio setting bit for the prescaler
(8/9 or 16/17 for the SW
IF
, 64/65 or 128/129 for the SW
RF
)
: Phase control bit for the phase detector(IF : FC
IF
, RF : FC
RF
)
: LD/fout signal select bit
NOTE:
Data input with MSB first.
[Table. 1]
[Table. 4]
[Table. 5]
[Table. 6]
FC
IF/RF
LDS
[Table. 7]
[Table. 3]
N
7
N
8
19
N
9
20
N
10
21
N
11
22
23
IF/RF IF/RF
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