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參數(shù)資料
| 型號： | MB15F73UL |
| 廠商： | Fujitsu Limited |
| 英文描述： | ASSP Dual Serial Input PLL Frequency Synthesizer |
| 中文描述： | ASSP的雙串行輸入鎖相環(huán)頻率合成器 |
| 文件頁數(shù)： | 8/18頁 |
| 文件大小： | 155K |
| 代理商： | MB15F73UL |
8
MB15F73UL
Dec. 2000
Edition 2.0
n
FUNCTIONAL DESCRIPTIONS
The divide ratio can be calculated using the following equation:
f
VCO
= {(P x N) + A} x f
OSC
÷
R
f
VCO
:
P:
N:
A:
f
OSC
:
R:
Output frequency of external voltage controlled oscillator (VCO)
Preset divide ratio of dual modulus prescaler (8 or 16 for IF-PLL, 64 or 128 for RF-PLL)
Preset divide ratio of binary 11-bit programmable counter (3 to 2,047)
Preset divide ratio of binary 7-bit swallow counter (0
≤
A
≤
127, condition;A < N)
Reference oscillation frequency
Preset divide ratio of binary 14-bit programmable reference counter (3 to 16,383)
Serial Data Input
Serial data is entered using three pins, Data pin, Clock pin, and LE pin. Programmable dividers of IF/RF-PLL
sections, programmable reference dividers of IF/RF-PLL sections are controlled individually.
Serial data of binary data is entered through Data pin.
On a rising edge of clock, one bit of serial data is transferred into the shift register. On a rising edge of load enable
signal , the data stored in the shift register is transferred to one of latch of them depending upon the control bit data
setting.
Table1. Control Bit
Shift Register Configuration
Control bit
Destination of serial data
CN1
CN2
0
0
The programmable reference counter for the IF-PLL.
1
0
The programmable reference counter for the RF-PLL.
0
1
The programmable counter and the swallow counter for the IF-PLL
1
1
The programmable counter and the swallow counter for the RF-PLL
Programmable Reference Counter
C
N
1
1
2
T
1
3
R
1
4
R
2
5
R
3
6
R
4
7
R
5
8
R
6
9
R
7
10
R
8
11
R
9
12
R
10
13
R
11
14
R
12
15
R
13
16
R
14
17
LSB
MSB
Data Flow
C
N
2
T
2
18
CN1, 2
R1 to R14
T1, 2
CS
X
NOTE:
Data input with MSB first.
: Control bit [Table. 1]
: Divide ratio setting bits for the programmable reference counter (3 to 16,383) [Table. 2]
: LD/fout output setting bit
: Charge pump current select bit [Table. 8]
: Dummy bits(Set "0" or "1")
[Table. 3]
19
20
21
22
23
C
S
X
X
X
X
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| MB15F73UL_01 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:Dual Serial Input PLL Frequency Synthesizer |
| MB15F73ULPFT | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:Dual Serial Input PLL Frequency Synthesizer |
| MB15F73ULPFT-G-BNDE1 | 制造商:FUJITSU 功能描述: |
| MB15F73ULPFT-G-BND-EFE1 | 功能描述:IC SYNTHESIZR PLL DL INP 20TSSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:2,000 系列:- 類型:PLL 頻率合成器 PLL:是 輸入:晶體 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:1 差分 - 輸入:輸出:無/無 頻率 - 最大:1GHz 除法器/乘法器:是/無 電源電壓:4.5 V ~ 5.5 V 工作溫度:-20°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-LSSOP（0.175"，4.40mm 寬） 供應商設備封裝:16-SSOP 包裝:帶卷 (TR) 其它名稱:NJW1504V-TE1-NDNJW1504V-TE1TR |
| MB15F73ULPVA | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:Dual Serial Input PLL Frequency Synthesizer |
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