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參數(shù)資料
| 型號： | MB15F63UL |
| 廠商： | Fujitsu Limited |
| 英文描述： | Dual Serial Input PLL Frequency Synthesizer |
| 中文描述： | 雙串行輸入鎖相環(huán)頻率合成器 |
| 文件頁數(shù)： | 28/36頁 |
| 文件大小： | 231K |
| 代理商： | MB15F63UL |
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MB15F63UL
28
■
PRECAUTIONS FOR USE
The Fractional-N PLL used in the RF section is based on the
Σ
system and has the following characteristics.
(1) Integer operation when F = 0
When F is set to “0”, the
Σ
circuit block is stopped completely and the same operation as a normal Integer
product is performed. Therefore, the most preferable noise characteristics can be achieved.
(2) Generation of spurious signals
1.Spurious signals are generated in the offset part of fp, which is a comparison frequency (equivalent of a
reference leak in the integer type).
Example:
If fosc is set to 13 MHz and R is set to 2 when fvco is 800 MHz in the GSM 800 MHz band, Ntotal becomes
124 and F becomes 0. (Integer mode)
Spurious signals are generated at “fp / R = 13 MHz / 2 = 6.5 MHz” offset. (Reference leak)
(The waveform resembles that of the reference leakage shown on Ref Leakage of “REFERENCE INFORMA-
TION”. A filter can be used to eliminate the
effects.)
2. Due to the
Σ
circuit operation, spurious signals are generated where “F / Q
×
fp” or “(Q
F) / Q
×
fp”
is located.
Example:
fosc = 13 MHz; R = 2 in GSM 800 MHz band:
When fvco is 806.2 MHz, Ntotal becomes 142.0307692... and F becomes 32263. Consequently, spurious
signals are generated at “F / Q
×
fp : 200 kHz” offset.
Adjusting the filter may reduce these spurious signals. Furthermore, modifying R and fr may change the setting
value to avoid to generate spurious signals.
For example, when fosc = 13 MHz and R = 2, Ntotal becomes 125.0307692
…
, where fvco is 812.7 MHz.
Therefore, F becomes 32263. Spurious signals are supposed to be generated at “F / Q
×
fp : 200 kHz” and
200 kHz offset. However, if R is changed to 3, F will become 572683 and “F / Q
×
fp : 2.366 MHz” and
spurious signals will be the outer frequencies. Therefore, the effects will not be foreseen.
ATTEN 10 dB
RL 0 dBm
VAVG 20
10 dB/
MKR
82.50 dB
200.0 kHz
MKR
200.0 kHz
82.50 dB
D
S
CENTER 806.2000 MHz
RBW 1.0 kHz
SPAN 500.0 kHz
SWP 1.30 s
VBW 3.0 kHz
C/N 200 kHz Offset
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MB15F63ULPVA1 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:Dual Serial Input PLL Frequency Synthesizer |
| MB15F63ULPVA1-GE1 | 制造商:Fujitsu 功能描述:Bulk |
| MB15F72SP | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:Dual Serial Input PLL Frequency Synthesizer |
| MB15F72SPPFT | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:Dual Serial Input PLL Frequency Synthesizer |
| MB15F72SPPV | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:Dual Serial Input PLL Frequency Synthesizer |
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