參數(shù)資料
型號(hào): MB15F63UL
廠商: Fujitsu Limited
英文描述: Dual Serial Input PLL Frequency Synthesizer
中文描述: 雙串行輸入鎖相環(huán)頻率合成器
文件頁(yè)數(shù): 11/36頁(yè)
文件大?。?/td> 231K
代理商: MB15F63UL
MB15F63UL
11
c) Data bit description
Bit name
Description
F1RF to F20RF
Bits for setting the fractional numerator for the RF-PLL (Setting range: 0 to 1048575)
(Refer to Table 1)
A1RF to A4RF
Bits for setting the division ratio of the RF-side swallow counter (Setting range: 0 to 15)
(Refer to Table 2)
N1RF to N7RF
Bits for setting the RF-side main counter (Setting range: 5 to 127) (Refer to Table 3)
R1RF to R6RF
Bits for setting the division ratio of the RF-side reference counter (Setting range: 1 to 63)
(Refer to Table 4)
A1IF to A7IF
Bits for setting the division ratio of the IF-side swallow counter (Setting range: 0 to 127)
(Refer to Table 5)
N1IF to N11IF
Bits for setting the IF-side main counter (Setting range: 3 to 2047) (Refer to Table 6)
R1IF to R14IF
Bits for setting the division ratio of the IF-side reference counter (Setting range: 3 to 16383)
(Refer to Table 7)
TMC
Control bit for setting Speedup Mode (Refer to Table 9)
TMC_bit
=
“0”
disabled
TMC
_
bit
=
“1”
enabled
Bits for setting the speedup timer (Refer to Table 8)
TM1 to TM7
PSRF
Power saving bit for the RF-PLL section
FCRF
Phase switching bit for the RF-side phase comparator (Refer to Table 11)
ODSW
Control bit for the open-drain switch
ODSW bit
=
“0”
Dynamic
ODSW bit
=
“1”
OFF
Phase switching bit for the IF-side phase comparator (Refer to Table 11)
FCIF
CSIF
Charge pump switching bit for the IF-PLL section
CSIF bit
=
“0”
Icp
=
±
1.5mA
CSIF bit
=
“1”
Icp
=
±
6.0mA
Bits for setting the division ratio of the IF-side prescaler
SWIF
=
“0”
16/17
SWIF
=
“1”
8/9
Power saving bit for the IF-PLL section
SWIF
PSIF
LDS, T1, T2
Control bits for selecting monitor function (Refer to Table 10)
SC
Bit for switching the order of
Σ
SC bit
=
“0”
2nd order
SC bit
=
“1”
3rd order
Dummy bit: Must be fixed to “0”
×
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