參數(shù)資料
型號: MAXQ7670EVKIT+
廠商: Maxim Integrated Products
文件頁數(shù): 37/38頁
文件大?。?/td> 0K
描述: KIT EVAL FOR MAXQ7670
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 1
系列: MAXQ®
類型: MCU
適用于相關(guān)產(chǎn)品: MAXQ7670
所含物品:
MAXQ7670
Microcontroller with 10-Bit ADC,
PGA, 64KB Flash, and CAN Interface
8
_______________________________________________________________________________________
Note 1:
All devices are 100% production tested at TA = +25°C and +125°C. Temperature limits to TA = -40°C are guaranteed by
design.
Note 2:
All analog functions disabled and all digital inputs connected to supply or ground.
Note 3:
High-speed/8 mode without CAN; VDVDD = +2.5V, CPU and 16-bit timer running at 2MHz from an external, 16MHz crystal
oscillator; all other peripherals disabled; all digital I/Os static at VDVDDIO or GNDIO; TA = TMIN to TMAX.
Note 4:
High-speed/1 mode with CAN; VDVDD = +2.5V, CPU and 16-bit timer running at 16MHz from an external, 16MHz crystal
oscillator; CAN enabled and communicating at 500kbps; all other peripherals disabled, all digital I/Os (except CANTXD
and CANRXD) static at VDVDDIO or GNDIO, TA = TMIN to TMAX.
Note 5:
Low speed, PMM1 mode without CAN; VDVDD = +2.5V, CPU and one timer running from an external, 16MHz crystal oscilla-
tor in PMM1 mode; all other peripherals disabled; all digital I/Os static at VDVDDIO or GNDIO, TA = TMIN to TMAX.
Note 6:
CAN transmitting at 500kbps; 16-bit timer output switching at 500kHz; all active I/Os are loaded with a 20pF capacitor; all
remaining digital I/Os are static at VDVDDIO or GNDIO, TA = TMIN to TMAX.
Note 7:
Guaranteed by design and characterization.
Note 8:
This is not a static capacitance. It is the capacitance presented to the analog input when the T/H amplifier is in sample mode.
Note 9:
The switched capacitor on the REFADC input can disturb the reference voltage. To reduce this disturbance, place a 0.1F
capacitor from REFADC to AGND as close as possible to REFADC.
Note 10: The digital design is fully static. However, the lower clock limit is set by a clock detect circuit. The MAXQ7670 switches to
the internal RC clock if the external input goes below 166kHz. This clock detect circuit also acts to detect a crystal failure
when a crystal is used.
ELECTRICAL CHARACTERISTICS (continued)
(VDVDDIO = +5.0V, VAVDD = +3.3V, VDVDD = +2.5V, VREFADC = +3.3V, system clock = 16MHz. TA = TMIN to TMAX, unless otherwise
noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SS Falling Edge to First SCLK
Sample Edge
tSSE
2 tSYSCLK
+ 5
ns
SCLK Inactive to
SS Rising
Edge
tSD
tSYSCLK
+ 10
ns
Minimum
CS Pulse Width
tSCW
tSYSCLK
+ 10
ns
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