參數(shù)資料
型號(hào)： MAX9856ETL+
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 19/46頁(yè)
文件大?。?/td> 0K
描述： IC CODEC AUDIO LP 40TQFN-EP
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 50
類型： 音頻編解碼器
數(shù)據(jù)接口： 串行
分辨率（位）： 18 b
ADC / DAC 數(shù)量： 2 / 2
三角積分調(diào)變： 是
S/N 比，標(biāo)準(zhǔn) ADC / DAC (db)： 77 / 91
動(dòng)態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db)： 85 / 91
電壓 - 電源，模擬： 1.71 V ~ 3.6 V
電壓 - 電源，數(shù)字： 1.71 V ~ 3.6 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 40-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 40-TQFN-EP（5x5）
包裝： 管件
產(chǎn)品目錄頁(yè)面： 1392 (CN2011-ZH PDF)
MAX9856
Low-Power Audio CODEC with
DirectDrive Headphone Amplifiers
26
______________________________________________________________________________________
REGISTER
FUNCTION
APIN
LRCLK_A/GPIO Configuration:
00 = General-purpose input
01 = Word clock for the ADC
10 = General-purpose output—low
11 = General-purpose output—high
When APIN
≠ 01, LRCLK_D is used as the word clock for both the DAC and ADC. AWCI, ABCI, and
ADLY are still active and independent from the DAC mode bit settings when operating with a shared
LRCLK_D.
ADLY
ADC Data Delay
0—The most significant bit of an audio word is valid at the first BCLK edge after the LRCLK_A
transition.
1—The most significant bit of an audio word is valid at the second BCLK edge after the LRCLK_A
transition.
(ADLY = 1 for I2S-compatible mode)
APLLEN
ADC PLL Enable. This bit only applies when APIN = 01. When APIN
≠ 01 use DPLLEN for both the
DAC and ADC:
0 (Valid for slave and master mode)—The frequency of LRCLK_A is set by the ADCNI divider bits. In
master mode, the MAX9856 generates LRCLK_A using the specified divide ratio. In slave mode, the
MAX9856 expects an LRCLK_A using specified divide ratio.
1 (Valid for slave mode only)—A digital PLL locks on to any externally supplied LRCLK_A signal
regardless of the MCLK frequency.
ADCNI
ADC LRCLK Divider. If APIN
≠ 01, use DACNI for both the DAC and ADC. When APLLEN is set low,
the frequency of LRCLK_A is determined by ADCNI. See Table 6 for common ADCNI values:
ADCNI = (65536 x 96 x fLRCLK_A)/fPCLK.
fLRCLK_A = LRCLK_A frequency.
fPCLK = Prescaled MCLK internal clock frequency (PCLK).
ADC Output Gain. Specifies the gain applied to the digital output of the ADC prior to being output
from the device.
VALUE
GAIN (dB)
0x0
+3
0x1
+2
0x2
+1
0x3
0
0x4
-1
0x5
-2
0x6
-3
0x7
-4
0x8
-5
0x9
-6
0xA
-7
0xB
-8
0xC
-9
0xD
-10
0xE
-11
AGAIN
0xF
-12
ADC Interface Register Bit Description (continued)
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MAX9856ETL/V+ 功能描述:接口—CODEC Low-Power Audio Codec With Directdrive. Headphone Amplifiers RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel
MAX9856ETL/V+T 功能描述:接口—CODEC Low-Power Audio Codec With Directdrive. Headphone Amplifiers RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel
MAX9856ETL+ 功能描述:接口—CODEC Stereo Audio CODEC w/DirectDrive Amp RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel
MAX9856ETL+T 功能描述:接口—CODEC Stereo Audio CODEC w/DirectDrive Amp RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel
MAX9856EVKIT+ 功能描述:音頻 IC 開發(fā)工具 Evaluation Kit for the MAX9856 RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Kits 類型:Audio Amplifiers 工具用于評(píng)估:TAS5614L 工作電源電壓:12 V to 38 V
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