參數(shù)資料
型號(hào): MAX98088EWY+T
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 6/123頁(yè)
文件大?。?/td> 0K
描述: IC CODEC AUDIO FLEXSOUND 63WLP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
類型: 立體聲音頻
數(shù)據(jù)接口: I²C,I²S,串行,SPI?
分辨率(位): 24 b
ADC / DAC 數(shù)量: 2 / 2
三角積分調(diào)變: 無(wú)
S/N 比,標(biāo)準(zhǔn) ADC / DAC (db): 93 / 101
動(dòng)態(tài)范圍,標(biāo)準(zhǔn) ADC / DAC (db): 93 / 101
電壓 - 電源,模擬: 1.65 V ~ 2 V
電壓 - 電源,數(shù)字: 1.65 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 63-WFBGA,WLCSP
供應(yīng)商設(shè)備封裝: 63-WLP
包裝: 帶卷 (TR)
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Maxim Integrated Products 103
MAX98088
Stereo Audio Codec
with FlexSound Technology
Headphone
DirectDrive Headphone Amplifier
Traditional single-supply headphone amplifiers have
outputs biased at a nominal DC voltage (typically half
the supply). Large coupling capacitors are needed to
block this DC bias from the headphone. Without these
capacitors, a significant amount of DC current flows to
the headphone, resulting in unnecessary power dis-
sipation and possible damage to both headphone and
headphone amplifier.
Maxim’s second-generation DirectDrive architecture
uses a charge pump to create an internal negative sup-
ply voltage. This allows the headphone outputs of the ICs
to be biased at GND while operating from a single supply
(Figure 28). Without a DC component, there is no need
for the large DC-blocking capacitors. Instead of two large
(220F typ) capacitors, the IC’s charge pump requires
3 small ceramic capacitors, conserving board space,
reducing cost, and improving the frequency response of
the headphone amplifier.
Charge Pump
The dual-mode charge pump generates both the positive
and negative power supply for the headphone amplifier.
To maximize efficiency, both the charge pump’s switching
frequency and output voltage change based on signal
level.
When the input signal level is less than 10% of PVDD,
the switching frequency is reduced to a low rate. This
minimizes switching losses in the charge pump. When
the input signal exceeds 10% of PVDD, the switching fre-
quency increases to support the load current.
For input signals below 25% of PVDD, the charge pump
generates Q(PVDD/2) to minimize the voltage drop
across the amplifier’s power stage and thus improve
efficiency. Input signals that exceed 25% of PVDD cause
the charge pump to output QPVDD. The higher output
voltage allows for full output power from the headphone
amplifier.
To prevent audible gliches when transitioning from the
Q
(PVDD/2) output mode to the QPVDD output mode, the
charge pump transitions very quickly. This quick change
draws significant current from PVDD for the duration of
the transition. The bypass capacitor on PVDD supplies
the required current and prevents droop on PVDD.
The charge pump’s dynamic switching mode can be
turned off through the I2C interface. The charge pump
can then be forced to output either Q(PVDD/2) or QPVDD
regardless of input signal level.
Table 26. Distortion Limiter Registers
REGISTER
BIT
NAME
DESCRIPTION
0x46
7
THDCLP
Distortion Limit
Measured in % THD+N.
6
VALUE
THD+N LIMIT (%)
VALUE
THD+N LIMIT (%)
0x0
Limiter disabled
0x8
12
5
0x1
< 1
0x9
14
0x2
1
0xA
16
0x3
2
0xB
18
4
0x4
4
0xC
20
0x5
6
0xD
21
0x6
8
0xE
22
0x7
10
0xF
24
0
THDT1
Distortion Limiter Release Time Constant
Duration of time required for the speaker amplifier’s output gain to adjust back to the
nominal level after a large signal has passed.
0 = 1.4s
1 = 2.8s
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