參數(shù)資料
型號： MAX98088EWY+T
廠商： Maxim Integrated Products
文件頁數(shù)： 104/123頁
文件大?。?/td> 0K
描述： IC CODEC AUDIO FLEXSOUND 63WLP
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 2,500
類型： 立體聲音頻
數(shù)據(jù)接口： I²C，I²S，串行，SPI?
分辨率（位）： 24 b
ADC / DAC 數(shù)量： 2 / 2
三角積分調(diào)變： 無
S/N 比，標(biāo)準(zhǔn) ADC / DAC (db)： 93 / 101
動態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db)： 93 / 101
電壓 - 電源，模擬： 1.65 V ~ 2 V
電壓 - 電源，數(shù)字： 1.65 V ~ 3.6 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 63-WFBGA，WLCSP
供應(yīng)商設(shè)備封裝： 63-WLP
包裝： 帶卷 (TR)
Maxim Integrated Products 81
MAX98088
Stereo Audio Codec
with FlexSound Technology
Clock Control
The digital signal paths in the IC require a master clock
(MCLK) between 10MHz and 60MHz to function. The
MAX98088 requires an internal clock between 10MHz
and 20MHz. A prescaler divides MCLK by 1, 2, or 4 to
create the internal clock (PCLK). PCLK is used to clock
all portions of the IC.
The MAX98088 includes two digital audio signal paths,
both capable of supporting any sample rate from 8kHz
to 96kHz. Each path is independently configured to allow
different sample rates. To accommodate a wide range
of system architectures, four main clocking modes are
supported:
U
PLL Mode: When operating in slave mode, enable the
PLL to lock onto any LRCLK input. This mode requires
the least configuration, but provides the lowest per-
formance. Use this mode to simplify initial setup or
when normal mode and exact integer mode cannot
be used.
U
Normal Mode: This mode uses a 15-bit clock divider
to set the sample rate relative to PCLK. This allows
high flexibility in both the PCLK and LRCLK frequen-
cies and can be used in either master or slave mode.
U
Exact Integer Mode (DAI1 only): In both master and
slave modes, common MCLK frequencies (12MHz,
13MHz, 16MHz, and 19.2MHz) can be programmed
to operate in exact integer mode for both 8kHz and
16kHz sample rates. In these modes, the MCLK and
LRCLK rates are selected by using the FREQ1 bits
instead of the NI, and PLL control bits.
U
DAC Low-Power Mode: This mode bypasses the
PLL for reduce power consumptions and uses fixed
counters to generate the clocks. The DAI__DAC_LP
bits override the other clock settings.
Table 11. Clock Control Registers
REGISTER
BIT
NAME
DESCRIPTION
0x10
5
PSCLK
MCLK Prescaler
Generates PCLK, which is used by all internal circuitry.
00 = PCLK disabled
01 = 10MHz P MCLK P 20MHz (PCLK = MCLK)
10 = 20MHz P MCLK P 40MHz (PCLK = MCLK/2)
11 = 40MHz P MCLK P 60MHz (PCLK = MCLK/4)
4
0x11/0x19
7
SR1/SR2
DAI1/DAI2 Sample Rate
Used by the ALC to correctly set the dual-band crossover frequency and the excursion
limiter to set the predefined corner frequencies.
6
VALUE
SAMPLE RATE
(kHz)
VALUE
SAMPLE RATE
(kHz)
0x0
Reserved
0x8
48
5
0x1
8
0x9
88.2
0x2
11.025
0xA
96
0x3
16
0xB
Reserved
0x4
22.05
0xC
Reserved
4
0x5
24
0xD
Reserved
0x6
32
0xE
Reserved
0x7
44.1
0xF
Reserved
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MAX98089ETN+ 功能描述:接口—CODEC Audio Codec RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel
MAX98089ETN+T 功能描述:接口—CODEC Audio Codec RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel
MAX98089EVKIT#TQFN 功能描述:音頻 IC 開發(fā)工具 MAX98089 Eval Kit RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Kits 類型:Audio Amplifiers 工具用于評估:TAS5614L 工作電源電壓:12 V to 38 V
MAX98089EVKIT#WLP 功能描述:音頻 IC 開發(fā)工具 MAX98089 Eval Kit RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Kits 類型:Audio Amplifiers 工具用于評估:TAS5614L 工作電源電壓:12 V to 38 V
MAX98089EVKIT+TQFN 功能描述:音頻 IC 開發(fā)工具 RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Kits 類型:Audio Amplifiers 工具用于評估:TAS5614L 工作電源電壓:12 V to 38 V
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