參數(shù)資料
型號: MAX9568EEE+
廠商: Maxim Integrated Products
文件頁數(shù): 4/16頁
文件大小: 0K
描述: IC SYNC SEPARATOR ANLG 16-QSOP
標準包裝: 100
類型: 視頻同步分離器
應(yīng)用: 視頻數(shù)字轉(zhuǎn)換器
安裝類型: 表面貼裝
封裝/外殼: 16-SSOP(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 16-QSOP
包裝: 管件
MAX9568
Component Analog TV Sync Separator
12
______________________________________________________________________________________
Detailed Description
The MAX9568 sync separator extracts sync timing
information from SDTV, EDTV, and HDTV component
video signals. The MAX9568 is a stand-alone device,
and requires no external components to set timing or
bias voltage. The MAX9568 has high input impedance,
eliminating the need for a low-impedance video source
at the input.
The MAX9568 provides composite sync, vertical sync,
and horizontal sync outputs. The MAX9568 provides
automatic SDTV, EDTV, and HDTV detection logic out-
puts to indicate the type of TV standard being
processed. The MAX9568 provides a back-porch clamp
output signal.
The MAX9568 provides a loss-of-sync output to indi-
cate a loss-of-video input signal. The MAX9568 pro-
vides an output to indicate odd and even fields. The
MAX9568 provides a vertical interval coast output
which allows control of a PLL oscillator when coasting
through the vertical interval.
Component Video Input (CVIDIN)
CVIDIN provides a high input impedance to the analog
video source. This eliminates the requirement for a low-
impedance video source. Following the input buffer is
the sync slicer block. This block establishes a DC level
for the incoming video signal. The sync information is
stripped by using a comparator with threshold or slice
level that automatically adjusts to the incoming signal.
When the incoming signal has bilevel syncs, the slice is
made 95mV above the sync tip. When the incoming
signal has trilevel syncs, the slice is made 145mV
above the sync tip. The device’s wide dynamic range,
0.2V to VCC - 0.2V, allows the video signal from 0.5VP-P
to 2VP-P to be processed and operate in the linear
range. The mentioned threshold levels are independent
of the signal amplitude.
CVIDIN is biased to 0.35 x VCC through a 300kΩ resis-
tor. Use a 0.1F capacitor to AC-couple at the input if
the input signal is not within the input-voltage range, as
shown Figure 3.
VCC - 0.2V
2V (+6dB)
1V (0dB)
0.5V (-6dB)
2V (+6dB)
0.5V (-6dB)
0.2V
2.7V < VCC < 5.5V
INPUT-VOLTAGE RANGE MATRIX
Figure 3. Input-Voltage Range Matrix
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