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參數(shù)資料
| 型號(hào)： | MAX9485EUP+ |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 11/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK GEN PROG 20TSSOP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 74 |
| 類型： | 時(shí)鐘發(fā)生器 |
| PLL： | 是 |
| 輸入： | LVCMOS，LVTTL，晶體 |
| 輸出： | LVCMOS，LVTTL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:3 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 73.728MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-TSSOP |
| 包裝： | 管件 |
MAX9485
Programmable Audio Clock Generator
4
_______________________________________________________________________________________
Note 1: All parameters tested at TA = +25°C. Specifications over temperature are guaranteed by design and characterization.
Note 2: When X1 is used as an external reference.
Note 3: Guaranteed by design and characterization; limits are set at ±6 sigma.
Note 4: Includes crystal accuracy.
Note 5: FXTL = 27MHz. Nominal frequency.
Note 6: See frequency selection paragraph in the Applications Information section.
Note 7: A master device must provide a hold time of at least 300ns for the SDA signal (referred to VIL of the SCL signal) in order to
bridge the undefined region of SCL’s falling edge.
Note 8: Cb = total capacitance of one bus line in pF. tR and tF measured between 0.3 VDD and 0.7 VDD.
Note 9: Bus sink current is less than 6mA. Cb = total capacitance of one bus line in pF. tR and tF measured between 0.3 VDD and
0.7 VDD.
Note 10: Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns.
I2C TIMING CHARACTERISTICS
(VDD = VDD_P = 3.0V to 3.6V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C, VDD = VDD_P = 3.3V;
Figure 7.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Serial Clock
fSCL
400
kHz
Bus Free Time Between a STOP and
a START Condition
tBUF
1.3
s
Hold Time (Repeated) START
Condition
tHD, STA
0.6
s
Repeated START Condition Setup
Time
tSU, STA
0.6
s
STOP Condition Setup Time
tSU, STO
0.6
s
Data Hold Time
tHD,DAT
(Note 7)
0.05
0.9
s
Data Setup Time
tSU,DAT
100
ns
SCL Clock Low Period
tLOW
1.3
s
SCL Clock High Period
tHIGH
0.6
s
Rise Time of SDA and SCL, Receiving
tR
(Notes 3, 8)
20 + 0.1Cb
300
ns
Fall Time of SDA and SCL, Receiving
tF
(Notes 3, 8)
20 + 0.1Cb
300
ns
Fall Time of SDA, Transmitting
tF
(Notes 8, 9)
20 + 0.1Cb
250
ns
Pulse Width of Spike Suppressed
tSP
(Notes 3, 10)
0
50
ns
Capacitive Load for Each Bus Line
Cb
400
pF
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MAX9485EUP+ | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 Programmable Audio Clock Generator RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MAX9485EUP+T | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 Programmable Audio Clock Generator RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MAX9485EUP-T | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MAX9485EVKIT | 制造商:Maxim Integrated Products 功能描述:PROGRAMMABLE AUDIO CLOCK GENERATOR - Bulk |
| MAX9486EUG | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 35.328MHz Clock Synthesizer RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
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