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參數(shù)資料
| 型號(hào)： | MAX9406ETM+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 9/11頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DVI/HDMI LVL SHIFTR 48TQFN-EP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類型： | 電平移位器 |
| 應(yīng)用： | 基站 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-WFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 48-TQFN-EP（7x7） |
| 包裝： | 帶卷 (TR) |
MAX9406
DisplayPort to DVI/HDMI Level Shifter
_______________________________________________________________________________________
7
Printed-Circuit Board (PCB) Traces
Input and output trace characteristics affect the perfor-
mance of the MAX9406. Connect each of the inputs
and outputs to a 50
Ω characteristic impedance trace.
Avoid discontinuities in differential impedance and
maximize common-mode noise immunity by maintain-
ing the distance between differential traces, avoiding
sharp corners. Minimize the number of vias to prevent
impedance discontinuities. Reduce reflections by main-
taining the 50
Ω characteristic impedance through con-
nectors and across cables. Minimize skew by matching
the electrical length of the traces.
Exposed Paddle
The thin QFN packages used for the MAX9406 have
exposed paddles on the bottom. Connect the exposed
paddle to ground using a landing pad large enough to
accommodate the entire exposed paddle. Add vias
from the exposed paddle's land area to a copper poly-
gon on the other side of the PCB to provide lower ther-
mal impedance from the MAX9406 to the ambient air.
Chip Information
PROCESS: BiPolar
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