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參數(shù)資料
| 型號(hào)： | MAX9325EQI+T |
| 廠商： | Maxim Integrated Products |
| 文件頁(yè)數(shù)： | 12/12頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC CLK/DATA BUFF MUX 2:8 28-PLCC |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 500 |
| 類型： | 扇出緩沖器（分配），多路復(fù)用器，數(shù)據(jù) |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:8 |
| 差分 - 輸入:輸出： | 是/是 |
| 輸入： | HSTL，LVECL，LVPECL |
| 輸出： | LVECL，LVPECL |
| 頻率 - 最大： | 700MHz |
| 電源電壓： | 2.375 V ~ 3.8 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 28-PLCC（11.51x11.51） |
| 包裝： | 帶卷 (TR) |
MAX9325
2:8 Differential LVPECL/LVECL/HSTL Clock and
Data Driver
_______________________________________________________________________________________
9
Detailed Description
The MAX9325 low-skew, 2:8 differential driver features
extremely low output-to-output skew (50ps max) and
part-to-part skew (225ps max). These features make the
device ideal for clock and data distribution across a
backplane or board. The device selects one of the two
differential HSTL or LVECL/LVPECL inputs, and repeats
them at eight differential outputs. Outputs are compati-
ble with LVECL and LVPECL, and can directly drive 50
terminated transmission lines.
A 2:1 mux selects between the two differential inputs,
CLK0, CLK0 and CLK1, CLK1. The 2:1 mux is switched
by the single-ended CLK_SEL input. A logic low selects
the CLK0, CLK0 input. A logic high selects the CLK1,
CLK1 input. The logic threshold for CLK_SEL is set by
an internal VBB voltage reference. The selected input is
reproduced at eight differential outputs at speeds up to
700MHz.
The differential inputs can be configured to accept a
single-ended signal when the unused complementary
input is connected to the on-chip reference output volt-
age (VBB). A single-ended input of at least VBB ±95mV
or a differential input of at least 95mV switches the out-
puts to the VOH and VOL levels specified in the DC
Electrical Characteristics. The maximum magnitude of
the differential input from CLK_ to CLK_ is ±3.0V or
±(VCC - VEE), whichever is less. This limit also applies
to the difference between a single-ended input and any
reference voltage input.
The single-ended CLK_SEL input has a 75k pulldown
to VEE that selects the default input, CLK0, CLK0, when
CLK_SEL is left open or at VEE. All the differential inputs
have 105k pulldowns to VEE. Internal pulldowns and a
fail-safe circuit ensure differential low default outputs
when the inputs are left open or at VEE.
Specifications for the high and low voltages of a differ-
ential input (VIHD and VILD) and the differential input
voltage (VIHD - VILD) apply simultaneously.
For interfacing to differential HSTL and LVPECL signals,
these devices operate over a +2.375V to +3.8V supply
range, allowing high-performance clock or data distrib-
ution in systems with a nominal +2.5V or +3.3V supply.
For differential LVECL operation, these devices operate
from a -2.375V to -3.8V supply.
Single-Ended Operation
CLK_SEL is a single-ended input with the input threshold
internally set to VBB, and can be driven to VCC or VEE or
by a single-ended LVPECL/LVECL signal. The CLK_,
CLK_ are differential inputs but can be configured to
accept single-ended inputs when operating at supply
voltages greater than 2.58V. The recommended supply
voltage for single-ended operation is 3.0V to 3.8V. A dif-
OR
VBB
tPLH
tPHL
VOH - VOL
Q_
CLK_ WHEN CLK_ = VBB
VOH
VIL
VIH
VOL
CLK_ WHEN CLK_ = VBB
Figure 3. Single-Ended Input (CLK_, CLK_) to Output (Q_, Q_) Delay Timing Diagram
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相關(guān)代理商/技術(shù)參數(shù) |
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| MAX9325EVKIT | 制造商:Maxim Integrated Products 功能描述:2:8 DIFFERENTIAL LVPECL/LVECL/HSTL CLOCK AND DATA DRIVER - Boxed Product (Development Kits) |
| MAX9326EGI | 制造商:Rochester Electronics LLC 功能描述: 制造商:Maxim Integrated Products 功能描述: |
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| MAX9326EQI+ | 制造商:Maxim Integrated Products 功能描述:CLOCK AND DATA DRVR 28PLCC - Rail/Tube |
| MAX9326EQI+T | 制造商:Maxim Integrated Products 功能描述:CLOCK AND DATA DRVR 28PLCC - Tape and Reel |
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