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參數(shù)資料
| 型號： | MAX9325EQI+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 10/12頁 |
| 文件大小： | 0K |
| 描述： | IC CLK/DATA BUFF MUX 2:8 28-PLCC |
| 產(chǎn)品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 500 |
| 類型： | 扇出緩沖器（分配），多路復用器，數(shù)據(jù) |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:8 |
| 差分 - 輸入:輸出： | 是/是 |
| 輸入： | HSTL，LVECL，LVPECL |
| 輸出： | LVECL，LVPECL |
| 頻率 - 最大： | 700MHz |
| 電源電壓： | 2.375 V ~ 3.8 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-LCC（J 形引線） |
| 供應商設備封裝： | 28-PLCC（11.51x11.51） |
| 包裝： | 帶卷 (TR) |
MAX9325
2:8 Differential LVPECL/LVECL/HSTL Clock and
Data Driver
_______________________________________________________________________________________
7
Pin Description
PIN
PLCC
QFN
NAME
FUNCTION
1, 8, 15, 22
4, 11, 18, 25
VCC
Positive Supply Voltage. Bypass each VCC to VEE with 0.1F and 0.01F ceramic
capacitors. Place the capacitors as close to the device as possible, with the smaller
value capacitor closest to the device.
25
CLK0
Inverting Differential Clock Input 0. Internal 105k
pulldown to VEE.
36
VBB
Reference Output Voltage. Connect to the inverting or noninverting clock input to
provide a reference for single-ended operation. When used, bypass VBB to VCC with a
0.01F ceramic capacitor. Otherwise leave open.
47
CLK1
Noninverting Differential Clock Input 1. Internal 105k
pulldown to VEE.
58
CLK1
Inverting Differential Clock Input 1. Internal 105k
pulldown to VEE.
69
N.C.
Not Connected
710
Q7
Inverting Q7 Output. Typically terminate with 50
resistor to VCC - 2V.
912Q7
Noninverting Q7 Output. Typically terminate with 50
resistor to VCC - 2V.
10
13
Q6
Inverting Q6 Output. Typically terminate with 50
resistor to VCC - 2V.
11
14
Q6
Noninverting Q6 Output. Typically terminate with 50
resistor to VCC - 2V.
12
15
Q5
Inverting Q5 Output. Typically terminate with 50
resistor to VCC - 2V.
13
16
Q5
Noninverting Q5 Output. Typically terminate with 50
resistor to VCC - 2V.
14
17
Q4
Inverting Q4 Output. Typically terminate with 50
resistor to VCC - 2V.
16
19
Q4
Noninverting Q4 Output. Typically terminate with 50
resistor to VCC - 2V.
17
20
Q3
Inverting Q3 Output. Typically terminate with 50
resistor to VCC - 2V.
18
21
Q3
Noninverting Q3 Output. Typically terminate with 50
resistor to VCC - 2V.
19
22
Q2
Inverting Q2 Output. Typically terminate with 50
resistor to VCC - 2V.
20
23
Q2
Noninverting Q2 Output. Typically terminate with 50
resistor to VCC - 2V.
21
24
Q1
Inverting Q1 Output. Typically terminate with 50
resistor to VCC - 2V.
23
26
Q1
Noninverting Q1 Output. Typically terminate with 50
resistor to VCC - 2V.
24
27
Q0
Inverting Q0 Output. Typically terminate with 50
resistor to VCC - 2V.
25
28
Q0
Noninverting Q0 Output. Typically terminate with 50
resistor to VCC - 2V.
26
1
VEE
Negative Supply Voltage
27
2
CLK_SEL
Clock Select Input. When driven low, the CLK0 input is selected. Drive high to select
the CLK1 Input. The CLK_SEL threshold is equal to VBB. Internal 75k
pulldown to VEE.
28
3
CLK0
Noninverting Differential Clock Input 0. Internal 105k
pulldown to VEE.
Exposed
Pad
—Internally Connected to VEE
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| MAX9326EQI+T | 制造商:Maxim Integrated Products 功能描述:CLOCK AND DATA DRVR 28PLCC - Tape and Reel |
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