參數(shù)資料
型號(hào): MAX9158
廠商: Maxim Integrated Products, Inc.
英文描述: Quad Bus LVDS Transceiver in 44 QFN
中文描述: 四路、總線式LVDS收發(fā)器,44 QFN封裝
文件頁(yè)數(shù): 8/15頁(yè)
文件大?。?/td> 358K
代理商: MAX9158
M
Detailed Description
The MAX9158 is a four-channel, 200Mbps, 3.3V BLVDS
transceiver in a 44-lead QFN package, ideal for driving
heavily loaded multipoint buses, typically 16 to 20
cards plugged into a backplane. The MAX9158
receivers accept a differential input and have a fail-safe
input circuit. The devices detect differential signals as
low as 100mV and as high as V
CC
.
The MAX9158 driver outputs use a current-steering
configuration to generate a 9.25mA to 17mA output
current. This current-steering approach induces less
ground bounce and no shoot-through current, enhanc-
ing noise margin and system speed performance. The
outputs are short-circuit current limited.
The MAX9158 current-steering output requires a resis-
tive load to terminate the signal and complete the trans-
mission loop. Because the devices switch the direction
of current flow and not voltage levels, the output volt-
age swing is determined by the value of the termination
resistor multiplied by the output current. With a typical
14.75mA output current, the MAX9158 produces a
398mV output voltage when driving a bus terminated
with two 54
resistors (14.75mA
27
= 398mV).
Logic states are determined by the direction of current
flow through the termination resistor.
Fail-Safe Receiver Inputs
The fail-safe feature of the MAX9158 sets the receiver
output high when the receiver differential input is:
Open
Undriven and shorted
Undriven and terminated
Without a fail-safe circuit, when the input is undriven,
noise at the input may switch the output and it may
appear to the system that data is being received. Open
or undriven terminated input conditions can occur
when a cable is disconnected or cut, or when a driver
is in high impedance. A shorted input can occur
because of a cable failure.
When the input is driven with a differential signal with a
common-mode voltage of 0.05V to 2.4V, the fail-safe
circuit is not activated. If the input is open, undriven
and shorted, or undriven and parallel terminated, an
internal resistor in the fail-safe circuit pulls both inputs
above V
CC
- 0.3V, activating the fail-safe circuit and
forcing the output high (Figure 1).
Effect of Capacitive Loading
The characteristic impedance of a differential PC board
trace is uniformly reduced when equal capacitive loads
are attached at equal intervals (provided the transition
time of the signal being driven on the trace is longer
than the delay between loads). This kind of loading is
typical of multipoint buses where cards are attached at
1in or 0.8in intervals along the length of a backplane.
The reduction in characteristic impedance is approxi-
mated by the following formula:
Z
DIFF
-loaded = Z
DIFF
-unloaded
SQRT [Co / (Co + N
C
L
/ L)]
where:
Z
DIFF
-unloaded = unloaded differential characteristic
impedance
Co = unloaded trace capacitance (pF/unit length)
C
L
= value of each capacitive load (pF)
N = number of capacitive loads
L = trace length
For example, if Co = 2.5pF/in, C
L
= 10pF, N = 18, L =
18in, and Z
DIFF
-unloaded = 120
, the loaded differen-
tial impedance is:
Z
DIFF
-loaded = 120
SQRT [2.5pF / (2.5pF + 18 x 10pF / 18in)]
ZDIFF-loaded = 54
In this example, capacitive loading reduces the charac-
teristic impedance from 120
to 54
. The load seen by
Quad Bus LVDS Transceiver in 44 QFN
8
_______________________________________________________________________________________
DO_+/RIN_+
V
CC
- 0.3V
D0_-/RIN_-
RO_
R
IN2
V
CC
R
IN1
R
IN1
MAX9158
Figure 1. Internal Fail-Safe Circuit
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