參數(shù)資料
型號(hào)： MAX9158
廠商： Maxim Integrated Products, Inc.
英文描述： Quad Bus LVDS Transceiver in 44 QFN
中文描述： 四路、總線式LVDS收發(fā)器，44 QFN封裝
文件頁(yè)數(shù)： 4/15頁(yè)
文件大?。?/td> 358K
代理商： MAX9158
M
Quad Bus LVDS Transceiver in 44 QFN
4
_______________________________________________________________________________________
AC ELECTRICAL CHARACTERISTICS
(V
CC
= 3.0V to 3.6V, R
L
= 27
±1%, receiver differential input voltage |V
ID
| = 0.15V to V
CC
, receiver input voltage range = 0V to V
CC
, input
frequency to differential inputs = 100MHz, input frequency to LVCMOS/LVTTL inputs = 100MHz, LVCMOS/LVTTL inputs = 0V to V
CC
with
2ns (10% to 90%) transition times. Differential input voltage transition time = 1ns (20% to 80%). Receiver input common-mode voltage
V
CM
= 0.075V to 2.4V, DE_ = high,
RE_
= low, T
A
= -40
°
C to +85
°
C, unless otherwise noted. Typical values are at V
CC
= 3.3V, |V
ID
| =
0.2V, V
CM
= 1.2V, and T
A
= +25
°
C.) (Notes 3 and 5)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DRIVER
Differential Propagation Delay
High to Low
t
PHLD
RE_
= high, C
L
= 10pF, Figures 3, 4
1.2
1.96
2.5
ns
Differential Propagation Delay
Low to High
t
PLHD
RE_
= high, C
L
= 10pF, Figures 3, 4
1.1
1.87
2.4
ns
Differential Skew | t
PHLD
- t
PLHD
|
(Note 6)
t
SKD1
RE_
= high, C
L
= 10pF, Figures 3, 4
91
250
ps
Channel-to-Channel Skew
(Note 7)
t
CCSK
RE_
= high, C
L
= 10pF, Figures 3, 4
119
350
ps
Chip-to-Chip Skew (Note 8)
Chip-to-Chip Skew (Note 9)
Rise Time
Fall Time
Disable Time High to Z
Disable Time Low to Z
Enable Time Z to High
Enable Time Z to Low
t
SKD2
T
SKD3
t
TLH
t
THL
t
PHZ
t
PLZ
t
PZH
t
PZL
RE_
= high, C
L
= 10pF, Figures 3, 4
RE_
= high, C
L
= 10pF, Figures 3, 4
RE_
= high, C
L
= 10pF, Figures 3, 4
RE_
= high, C
L
= 10pF, Figures 3, 4
RE_
= high, C
L
= 10pF, Figures 5, 6
RE_
= high, C
L
= 10pF, Figures 5, 6
RE_
= high, C
L
= 10pF, Figures 5, 6
RE_
= high, C
L
= 10pF, Figures 5, 6
0.45
0.90
1.4
1.4
1.4
5
5
6
6
ns
ns
ns
ns
ns
ns
ns
ns
0.6
0.6
1.07
1.10
2.8
2.8
4.6
4.5
Maximum Operating Frequency
(Note 10)
f
MAX
RE_
= high, C
L
= 10pF, Figures 5, 6
100
MHz
RECEIVER
Differential Propagation Delay
High to Low
t
PHLD
DE_ = low, Figures 7, 8; C
L
= 15pF
1.5
2.21
3.5
ns
Differential Propagation Delay
Low to High
t
PLHD
DE_ = low, Figures 7, 8; C
L
= 15pF
1.5
2.13
3.5
ns
Differential Skew | tPHLD -
tPLHD
| (Note 6)
t
SKD1
DE_ = low, Figures 7, 8; C
L
= 15pF
74
250
ps
Channel-to-Channel Skew
(Note 7)
t
CCSK
DE_ = low, Figures 7, 8; C
L
= 15pF
96
350
ps
Chip-to-Chip Skew (Note 8)
Chip-to-Chip Skew (Note 9)
Rise Time
t
SKD2
t
SKD3
t
TLH
DE_ = low, Figures 7, 8; C
L
= 15pF
DE_ = low, Figures 7, 8; C
L
= 15pF
DE_ = low, Figures 7, 8; C
L
= 15pF
0.63
1.6
2.0
1.6
ns
ns
ns
0.5
1.09
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