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參數(shù)資料
| 型號： | MAX9129EUE |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | Quad Bus LVDS Driver with Flow-Through Pinout |
| 中文描述： | QUAD LINE DRIVER, PDSO16 |
| 封裝： | 4.40 MM, TSSOP-16 |
| 文件頁數(shù)： | 8/13頁 |
| 文件大?。?/td> | 312K |
| 代理商： | MAX9129EUE |
M
The reduction in characteristic impedance is approxi-
mated by the following formula:
Z
DIFF-loaded
= Z
DIFF-unloaded
SQRT [C
o
/ (C
o
+ N
C
L
/ L)]
where:
Z
DIFF-unloaded
= unloaded differential characteristic im-
pedance
C
o
= unloaded trace capacitance (pF/unit length)
C
L
= value of each capacitive load (pF)
N = number of capacitive loads
L = trace length
For example, if C
o
= 2.5pF/in, C
L
= 10pF, N = 18, L =
18in, and Z
DIFF-unloaded
= 120
, the loaded differential
impedance is:
Z
DIFF-loaded
= 120
SQRT [2.5pF /
(2.5pF + 18
10pF/18in)]
Z
DIFF-loaded
= 54
In this example, capacitive loading reduces the charac-
teristic impedance from 120
to 54
. The load seen by
a driver located on a card in the middle of the bus is
27
because the driver sees two 54
loads in parallel.
A typical LVDS driver (rated for a 100
load) would not
develop a large enough differential signal to be reliably
detected by an LVDS receiver. Maxim
’
s BLVDS driver is
designed and specified to drive a 27
load to differen-
tial voltage levels of 250mV to 450mV (which are stan-
dard LVDS driver levels). A standard LVDS receiver is
able to detect this level of differential signal.
Short extensions off the bus, called stubs, contribute to
capacitive loading. Keep stubs less than 1in for a good
balance between ease of component placement and
good signal integrity.
The MAX9129 is a current source driver and drives
larger differential signal levels into loads higher than
27
and smaller levels into loads less than 27
(see
typical operating curves). To keep loading from reduc-
ing bus impedance below the rated 27
load, PC
board traces can be designed for higher unloaded
characteristic impedance.
Effect of Transition Time
For transition times (measured from 0% to 100%) short-
er than the delay between capacitive loads, the loads
are seen as low-impedance discontinuities from which
the driven signal is reflected. Reflections add and sub-
tract from the signal being driven and cause decreased
noise margin and jitter. The MAX9129 is designed for a
minimum transition time of 1ns (rated 0.6ns from 20% to
80%, or about 1ns 0% to 100%) to reduce reflections
while being fast enough for high-speed backplane data
transmission.
Power-On Reset
The power-on reset voltage of the MAX9129 is typically
2.25V. When the supply falls below this voltage, the
device is disabled and the outputs are in high imped-
ance.
Applications Information
Power-Supply Bypassing
Bypass V
CC
with high-frequency, surface-mount
ceramic 0.1μF and 0.001μF capacitors in parallel as
close to the device as possible, with the smaller valued
capacitor closest to V
CC
.
Termination
In the example above, the loaded differential imped-
ance of the bus is reduced to 54
. Since it can be dri-
ven from any card position, the bus must be terminated
at each end. A parallel termination of 54
at each end
of the bus placed across the traces that make up the
differential pair provides a proper termination. The total
load seen by the driver is 27
.
The MAX9129 drives higher differential signal levels
into lighter loads. A multidrop bus with the driver at one
end and receivers connected at regular intervals along
the bus has a lowered impedance due to capacitive
loading. Assuming the same impedance calculated in
the multidrop example above (54
), the multidrop bus
can be terminated with a single, parallel-connected
54
resistor at the far end from the driver. Only a single
resistor is required because the driver sees one 54
differential trace. The signal swing is larger with a 54
load.
In general, parallel terminate each end of the bus with a
resistor matching the differential impedance of the bus
(taking into account any reduced impedance due to
loading).
Board Layout
A four-layer PC board that provides separate power,
ground, input, and output signals is recommended.
Keep the LVTTL/LVCMOS and BLVDS signals separat-
ed to prevent coupling as shown in the suggested lay-
out for the QFN package (not drawn to scale) (Figure 6).
Quad Bus LVDS Driver with
Flow-Through Pinout
8
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相關代理商/技術參數(shù) |
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| MAX9129EUE+ | 功能描述:LVDS 接口集成電路 Quad LVDS Line Driver RoHS:否 制造商:Texas Instruments 激勵器數(shù)量:4 接收機數(shù)量:4 數(shù)據(jù)速率:155.5 Mbps 工作電源電壓:5 V 最大功率耗散:1025 mW 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-16 Narrow 封裝:Reel |
| MAX9129EUE+T | 功能描述:LVDS 接口集成電路 Quad LVDS Line Driver RoHS:否 制造商:Texas Instruments 激勵器數(shù)量:4 接收機數(shù)量:4 數(shù)據(jù)速率:155.5 Mbps 工作電源電壓:5 V 最大功率耗散:1025 mW 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-16 Narrow 封裝:Reel |
| MAX9129EUE-T | 功能描述:緩沖器和線路驅(qū)動器 RoHS:否 制造商:Micrel 輸入線路數(shù)量:1 輸出線路數(shù)量:2 極性:Non-Inverting 電源電壓-最大:+/- 5.5 V 電源電壓-最小:+/- 2.37 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Reel |
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| MAX912C/D | 功能描述:校驗器 IC RoHS:否 制造商:STMicroelectronics 產(chǎn)品: 比較器類型: 通道數(shù)量: 輸出類型:Push-Pull 電源電壓-最大:5.5 V 電源電壓-最小:1.1 V 補償電壓（最大值）:6 mV 電源電流（最大值）:1350 nA 響應時間: 最大工作溫度:+ 125 C 安裝風格:SMD/SMT 封裝 / 箱體:SC-70-5 封裝:Reel |
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