參數(shù)資料
型號: MAX8738EUA+T
廠商: Maxim Integrated Products
文件頁數(shù): 3/13頁
文件大?。?/td> 0K
描述: IC CALIBR TFT VCOM 8UMAX
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
類型: 視頻濾波器
應(yīng)用: LCD 顯示器
安裝類型: 表面貼裝
封裝/外殼: 8-TSSOP,8-MSOP(0.118",3.00mm 寬)
供應(yīng)商設(shè)備封裝: 8-uMAX
包裝: 帶卷 (TR)
Slave Address
After generating a START condition, the bus master
transmits the slave address consisting of a 7-bit device
code (0b0101111 or 5Eh) for the MAX8738. Since the
MAX8738 is a write-only device, the eighth bit of the
slave address is zero. The MAX8738 monitors the bus
for its corresponding slave address continuously. It
generates an acknowledge bit when it recognizes its
address.
SDA Data Valid
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal. The
data on the line must be changed during the LOW peri-
od of the clock signal. There is one clock pulse per bit
of data.
Acknowledge
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse that is associated with this acknowledge bit. The
device that acknowledges has to pull down the SDA
line during the acknowledge clock pulse so that the
SDA line is stable LOW during the HIGH period of the
acknowledge-related clock pulse. Of course, setup and
hold times must be taken into account. See Figure 7.
The MAX8738 does not acknowledge the program
EEPROM command (AAh) if HV is below 15.6V (typ) or
if the MAX8738 is not in program mode.
The MAX8738 does not acknowledge any command
while an internal programming cycle is in progress.
Once the internally timed EEPROM write cycle has
started, acknowledge polling can be initiated. This
involves repeatedly sending a 55h command. Only if
the internal write cycle has completed does the
MAX8738 acknowledge the command.
MAX8738
EEPROM-Programmable TFT VCOM
Calibrator with I2C Interface
______________________________________________________________________________________
11
SCL FROM
MASTER
DATA OUTPUT
BY MAX8738
DATA OUTPUT
BY MASTER
CLK1
START
CONDITION
S
1
CLK2
2
CLK8
8
CLK9
9
ACKNOWLEDGE
CLOCK PULSE
ACKNOWLEDGE
NOT ACKNOWLEDGE
D7
D6
D0
Figure 7. I2C Bus Acknowledge
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