參數(shù)資料
型號(hào): MAX7313AEG+T
廠商: Maxim Integrated Products
文件頁數(shù): 4/26頁
文件大?。?/td> 0K
描述: IC I/O EXPANDER I2C 16B 24QSOP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
接口: I²C
輸入/輸出數(shù): 16
中斷輸出:
頻率 - 時(shí)鐘: 400kHz
電源電壓: 2 V ~ 3.6 V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 24-SSOP(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 24-QSOP
包裝: 帶卷 (TR)
MAX7313
Command Address Autoincrementing
The command address stored in the MAX7313 circu-
lates around grouped register functions after each data
byte is written or read (Table 2).
Device Reset
If a device reset input is needed, consider the
MAX7314. The MAX7314 includes a RST input, which
clears any transaction to or from the MAX7314 on the
serial interface and configures the internal registers to
the same state as a power-up reset.
Detailed Description
Initial Power-Up
On power-up all control registers are reset and the
MAX7313 enters standby mode (Table 3). Power-up
status makes all ports into inputs and disables both the
PWM oscillator and blink functionality.
Configuration Register
The configuration register is used to configure the PWM
intensity mode, interrupt, and blink behavior, operate
the INT/O16 output, and read back the interrupt status
(Table 4).
16-Port I/O Expander with LED Intensity
Control, Interrupt, and Hot-Insertion Protection
12
______________________________________________________________________________________
Figure 10. Read, Write, and Interrupt Timing Diagrams
SLAVE ADDRESS
1
2
3
4567
89
S A6 A5 A4 A3 A2 A1 A00
A
0
00
COMMAND BYTE
1A
A
P
START CONDITION
ACKNOWLEDGE FROM SLAVE
STOP
CONDITION
P7–P0
P15– P8
DATA1 VALID
DATA2 VALID
SLAVE ADDRESS
1
2
3
4567
89
S A6A5A4A3A2A1A0
1
A
COMMAND BYTE
ANA
START CONDITION
ACKNOWLEDGE FROM SLAVE
ACKNOWLEDGE FROM MASTER
P7–P0
P15–P8
STOP CONDITION
P
NO ACKNOWLEDGE FROM
MASTER
DATA2
DATA4
DATA3
tDV
SLAVE ADDRESS
1
2
3
4567
89
S A6A5A4A3A2A1A0 1
A
COMMAND BYTE
ANA
START CONDITION
ACKNOWLEDGE FROM SLAVE
ACKNOWLEDGE FROM MASTER
P7–P0
P15–P8
STOP CONDITION
P
NO ACKNOWLEDGE FROM
MASTER
DATA1
DATA2
DATA3
DATA4
DATA6
DATA5
tDH
tDS
DATA1
tIV
tIR
tIV
SCL
SDA
SCL
SDA
SCL
SDA
WRITE TO OUTPUT PORTS REGISTERS (BLINK PHASE 0 REGISTERS/BLINK PHASE 1 REGISTERS)
READ FROM INPUT PORTS REGISTERS
INTERRUPT VALID/RESET
R/W
MSB
LSB
DATA1
MSB
LSB
DATA1
MSB
LSB
DATA2
MSB
LSB
DATA4
MSB
LSB
DATA6
MSB
LSB
DATA2
R/W
INT
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