參數(shù)資料
型號(hào)： MAX7313AEG+T
廠商： Maxim Integrated Products
文件頁數(shù)： 3/26頁
文件大?。?/td> 0K
描述： IC I/O EXPANDER I2C 16B 24QSOP
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 2,500
接口： I²C
輸入/輸出數(shù)： 16
中斷輸出： 是
頻率 - 時(shí)鐘： 400kHz
電源電壓： 2 V ~ 3.6 V
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： 24-SSOP（0.154"，3.90mm 寬）
供應(yīng)商設(shè)備封裝： 24-QSOP
包裝： 帶卷 (TR)
Any bytes received after the command byte are data
bytes. The first data byte goes into the internal register
of the MAX7313 selected by the command byte (Figure
8). If multiple data bytes are transmitted before a STOP
condition is detected, these bytes are generally stored
in subsequent MAX7313 internal registers because the
command byte address autoincrements (Table 2). A
diagram of a write to the output ports registers (blink
phase 0 registers or blink phase 1 registers) is given in
Figure 10.
Message Format for Reading
The MAX7313 is read using the MAX7313’s internally
stored command byte as an address pointer the same
way the stored command byte is used as an address
pointer for a write. The pointer autoincrements after
each data byte is read using the same rules as for a
write (Table 2). Thus, a read is initiated by first configur-
ing the MAX7313’s command byte by performing a
write (Figure 7). The master can now read n consecu-
tive bytes from the MAX7313 with the first data byte
being read from the register addressed by the initial-
ized command byte. When performing read-after-write
verification, remember to reset the command byte’s
address because the stored command byte address
has been autoincremented after the write (Table 2). A
diagram of a read from the input ports registers is
shown in Figure 10 reflecting the states of the ports.
Operation with Multiple Masters
If the MAX7313 is operated on a 2-wire interface with
multiple masters, a master reading the MAX7313 should
use a repeated start between the write, which sets the
MAX7313’s address pointer, and the read(s) that takes
the data from the location(s) (Table 2). This is because it
is possible for master 2 to take over the bus after master
1 has set up the MAX7313’s address pointer but before
master 1 has read the data. If master 2 subsequently
changes the MAX7313’s address pointer, then master
1’s delayed read can be from an unexpected location.
MAX7313
16-Port I/O Expander with LED Intensity
Control, Interrupt, and Hot-Insertion Protection
______________________________________________________________________________________
11
Figure 8. Command and Single Data Byte Received
SA
A
P
0
SLAVE ADDRESS
COMMAND BYTE
DATA BYTE
1
BYTE
AUTOINCREMENT MEMORY ADDRESS
D15 D14 D13 D12 D11 D10
D9
D8
D1
D0
D3
D2
D5
D4
D7
D6
ACKNOWLEDGE FROM MAX7313
HOW COMMAND BYTE AND DATA BYTE MAP INTO
MAX7313'S REGISTERS
R/W
Figure 9. n Data Bytes Received
SA
A
P
0
SLAVE ADDRESS
COMMAND BYTE
DATA BYTE
N
BYTES
AUTOINCREMENT MEMORY ADDRESS
D15 D14 D13 D12 D11 D10
D9
D8
D1
D0
D3
D2
D5
D4
D7
D6
ACKNOWLEDGE FROM MAX7313
HOW COMMAND BYTE AND DATA BYTE MAP INTO
MAX7313'S REGISTERS
R/W
Figure 7. Command Byte Received
SA
A
P
0
SLAVE ADDRESS
COMMAND BYTE
ACKNOWLEDGE FROM MAX7313
D15
D14
D13
D12
D11
D10
D9
D8
COMMAND BYTE IS STORED ON RECEIPT OF
STOP CONDITION
ACKNOWLEDGE FROM MAX7313
R/W
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