參數(shù)資料
型號(hào): MAX7300ATL+
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 6/20頁(yè)
文件大小: 0K
描述: IC I/O EXPANDER 2WIRE 40TQFN
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 50
接口: I²C,2 線串口
輸入/輸出數(shù): 28
中斷輸出:
頻率 - 時(shí)鐘: 400kHz
電源電壓: 2.5 V ~ 5.5 V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 40-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 40-TQFN-EP(6x6)
包裝: 管件
MAX7300
2-Wire-Interfaced, 2.5V to 5.5V, 20-Port or
28-Port I/O Expander
14
______________________________________________________________________________________
COMMAND ADDRESS
REGISTER
D15
D14
D13
D12
D11
D10
D9
D8
HEX
CODE
Port 26 only (data bit D0. D7-D1 read as 0)
X
0
1
0
1
0
0x3A
Port 27 only (data bit D0. D7-D1 read as 0)
X
0
1
0
1
0x3B
Port 28 only (data bit D0. D7-D1 read as 0)
X
0
1
0
0x3C
Port 29 only (data bit D0. D7-D1 read as 0)
X
0
1
0
1
0x3D
Port 30 only (data bit D0. D7-D1 read as 0)
X
0
1
0
0x3E
Port 31 only (data bit D0. D7-D1 read as 0)
X
0
1
0x3F
4 ports 4–7 (data bits D0–D3. D4–D7 read as 0)
X
1
0
0x40
5 ports 4–8 (data bits D0–D4. D5–D7 read as 0)
X
1
0
1
0x41
6 ports 4–9 (data bits D0–D5. D6–D7 read as 0)
X
1
0
1
0
0x42
7 ports 4–10 (data bits D0–D6. D7 reads as 0)
X
1
0
1
0x43
8 ports 4–11 (data bits D0–D7)
X
1
0
1
0
0x44
8 ports 5–12 (data bits D0–D7)
X
1
0
1
0
1
0x45
8 ports 6–13 (data bits D0–D7)
X
1
0
1
0
0x46
8 ports 7–14 (data bits D0–D7)
X
1
0
1
0x47
8 ports 8–15 (data bits D0–D7)
X
1
0
1
0
0x48
8 ports 9–16 (data bits D0–D7)
X
1
0
1
0
1
0x49
8 ports 10–17 (data bits D0–D7)
X
1
0
1
0
1
0
0x4A
8 ports 11–18 (data bits D0–D7)
X
1
0
1
0
1
0x4B
8 ports 12–19 (data bits D0–D7)
X
1
0
1
0
0x4C
8 ports 13–20 (data bits D0–D7)
X
1
0
1
0
1
0x4D
8 ports 14–21 (data bits D0–D7)
X
1
0
1
0
0x4E
8 ports 15–22 (data bits D0–D7)
X
1
0
1
0x4F
8 ports 16–23 (data bits D0–D7)
X
1
0
1
0
0x50
8 ports 17–24 (data bits D0–D7)
X
1
0
1
0
1
0x51
8 ports 18–25 (data bits D0–D7)
X
1
0
1
0
1
0
0x52
8 ports 19–26 (data bits D0–D7)
X
1
0
1
0
1
0x53
8 ports 20–27 (data bits D0–D7)
X
1
0
1
0
1
0
0x54
8 ports 21–28 (data bits D0–D7)
X
1
0
1
0
1
0
1
0x55
8 ports 22–29 (data bits D0–D7)
X
1
0
1
0
1
0
0x56
8 ports 23–30 (data bits D0–D7)
X
1
0
1
0
1
0x57
8 ports 24–31 (data bits D0–D7)
X
1
0
1
0
0x58
7 ports 25–31 (data bits D0–D6. D7 reads as 0)
X
1
0
1
0
1
0x59
6 ports 26–31 (data bits D0–D5. D6–D7 read as 0)
X
1
0
1
0
1
0
0x5A
5 ports 27–31 (data bits D0–D4. D5–D7 read as 0)
X
1
0
1
0
1
0x5B
4 ports 28–31 (data bits D0–D3. D4–D7 read as 0)
X
1
0
1
0
0x5C
3 ports 29–31 (data bits D0–D2. D3–D7 read as 0)
X
1
0
1
0
1
0x5D
2 ports 30–31 (data bits D0–D1. D2–D7 read as 0)
X
1
0
1
0
0x5E
1 port 31 only (data bits D0. D1–D7 read as 0)
X
1
0
1
0x5F
Table 5. Register Address Map (continued)
Note: Unused bits read as zero.
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