參數(shù)資料
型號: MAX7300ATL+
廠商: Maxim Integrated Products
文件頁數(shù): 14/20頁
文件大?。?/td> 0K
描述: IC I/O EXPANDER 2WIRE 40TQFN
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 50
接口: I²C,2 線串口
輸入/輸出數(shù): 28
中斷輸出:
頻率 - 時(shí)鐘: 400kHz
電源電壓: 2.5 V ~ 5.5 V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 40-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 40-TQFN-EP(6x6)
包裝: 管件
MAX7300
2-Wire-Interfaced, 2.5V to 5.5V, 20-Port or
28-Port I/O Expander
_______________________________________________________________________________________
3
ELECTRICAL CHARACTERISTICS (continued)
(
Typical Operating Circuit, VV+ = 2.5V to 5.5V, TA = TMIN to TMAX, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
GPIO outputs, ISOURCE = 2mA,
TA = -40°C to +85°C
V+ -
0.7
Output High Voltage
VOH
GPIO outputs, ISOURCE = 1mA,
TA = TMIN to TMAX (Note 2)
V+ -
0.7
V
Port Sink Current
IOL
VPORT = 0.6V
2
10
18
mA
Output Short-Circuit Current
IOLSC
Port configured output low, shorted to V+
2.75
11
20
mA
Input High-Voltage SDA, SCL,
AD0, AD1
VIH
0.7 x
V+
V
Input Low-Voltage SDA, SCL,
AD0, AD1
VIL
0.3 x
V+
V
Input Leakage Current SDA, SCL
IIH, IIL
-50
+50
nA
Input Capacitance
(Note 2)
10
pF
Output Low-Voltage SDA
VOL
ISINK = 6mA
0.4
V
TIMING CHARACTERISTICS (Figure 2)
(VV+ = 2.5V to 5.5V, TA = TMIN to TMAX, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Serial Clock Frequency
fSCL
400
kHz
Bus Free Time Between a STOP
and a START Condition
tBUF
1.3
s
Hold Time (Repeated) START
Condition
tHD, STA
0.6
s
Repeated START Condition
Setup Time
tSU, STA
0.6
s
STOP Condition Setup Time
tSU, STO
0.6
s
Data Hold Time
tHD, DAT
(Note 3)
15
900
ns
Data Setup Time
tSU, DAT
100
ns
SCL Clock Low Period
tLOW
1.3
s
SCL Clock High Period
tHIGH
0.7
s
Rise Time of Both SDA and SCL
Signals, Receiving
tR
(Notes 2, 4)
20 +
0.1Cb
300
ns
Fall Time of Both SDA and SCL
Signals, Receiving
tF
(Notes 2, 4)
20 +
0.1Cb
300
ns
Fall Time of SDA Transmitting
tF,TX
(Notes 2, 5)
20 +
0.1Cb
250
ns
Pulse Width of Spike Suppressed
tSP
(Notes 2, 6)
0
50
ns
Capacitive Load for Each Bus
Line
Cb
(Note 2)
400
pF
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