參數(shù)資料
型號: MAX6870ETJ-T
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: 電源管理
英文描述: EEPROM-Programmable Hex/Quad Power-Supply Sequencers/Supervisors with ADC
中文描述: 6-CHANNEL POWER SUPPLY MANAGEMENT CKT, QCC32
封裝: 7 X 7 MM, 0.80 MM HEIGHT, MO-220, TQFN-32
文件頁數(shù): 13/51頁
文件大小: 672K
代理商: MAX6870ETJ-T
MAX6870/MAX6871
Table 10 only applies to PO1 of the MAX6870. Write a 0
to a bit to make the PO1 output independent of the
respective signal (IN1–IN6 primary or secondary
thresholds, WDI1 or WDI2, GPI1–GPI4, MR, or other
programmable outputs).
EEPROM-Programmable Hex/Quad
Power-Supply Sequencers/Supervisors with ADC
20
______________________________________________________________________________________
Table 10. PO1 (MAX6870 Only) Output Dependency
REGISTER
ADDRESS
EEPROM
MEMORY
ADDRESS
BIT
OUTPUT ASSERTION CONDITIONS
[0]
1 = PO1 assertion depends on IN1 primary undervoltage threshold (Table 2).
[1]
1 = PO1 assertion depends on IN2 primary undervoltage threshold (Table 3).
[2]
1 = PO1 assertion depends on IN3 primary undervoltage threshold (Table 4).
[3]
1 = PO1 assertion depends on IN4 primary undervoltage threshold (Table 4).
[4]
1 = PO1 assertion depends on IN5 primary undervoltage threshold (Table 4).
[5]
1 = PO1 assertion depends on IN6 primary undervoltage threshold (Table 4).
[6]
1 = PO1 assertion depends on watchdog 1 (Tables 27 and 28).
0Eh
800Eh
[7]
1 = PO1 assertion depends on watchdog 2 (Tables 27 and 28).
[0]
1 = PO1 assertion depends on IN1 secondary undervoltage/overvoltage threshold (Table 2).
[1]
1 = PO1 assertion depends on IN2 secondary undervoltage/overvoltage threshold (Table 3).
[2]
1 = PO1 assertion depends on IN3 secondary undervoltage/overvoltage threshold (Table 4).
[3]
1 = PO1 assertion depends on IN4 secondary undervoltage/overvoltage threshold (Table 4).
[4]
1 = PO1 assertion depends on IN5 secondary undervoltage/overvoltage threshold (Table 4).
[5]
1 = PO1 assertion depends on IN6 secondary undervoltage/overvoltage threshold (Table 4).
[6]
1 = PO1 assertion depends on GPI1 (Table 6).
0Fh
800Fh
[7]
1 = PO1 assertion depends on GPI2 (Table 6).
[0]
1 = PO1 assertion depends on GPI3 (Table 6).
[1]
1 = PO1 assertion depends on GPI4 (Table 6).
[2]
1 = PO1 assertion depends on PO2 (Table 11).
[3]
1 = PO1 assertion depends on PO3 (Tables 12 and 13).
[4]
1 = PO1 assertion depends on PO4 (Tables 14 and 15).
[5]
1 = PO1 assertion depends on PO5 (Tables 16 and 17).
[6]
1 = PO1 assertion depends on PO6 (Tables 18 and 19).
10h
8010h
[7]
1 = PO1 assertion depends on PO7 (Table 20).
11h
8011h
[0]
1 = PO1 assertion depends on PO8 (Table 21).
40h
8040h
[0]
1 = PO1 asserts when MR = low (Table 7).
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