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| 型號(hào)： | MAX6853AEE-T |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | 顯示驅(qū)動(dòng)器 |
| 英文描述： | 2-Wire Interfaced, 5 x 7 Matrix Vacuum-Fluorescent Display Controller |
| 中文描述： | VACUUM FLUOR DISPLAY DRIVER, PDSO16 |
| 封裝： | 0.150 INCH, 0.25 MM PITCH, MO-137, QSOP-16 |
| 文件頁(yè)數(shù)： | 35/35頁(yè) |
| 文件大小： | 489K |
| 代理商： | MAX6853AEE-T |
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MAX6853
2-Wire Interfaced, 5
7 Matrix Vacuum-
Fluorescent Display Controller
_______________________________________________________________________________________
9
ber of digits (96/2 mode) against the availability of
annunciator segments (48/1 mode). Table 2 is the reg-
ister address map.
Initial Power-Up
Initial power-up resets all control registers, clears dis-
play segment and annunciator data, sets intensity to
minimum, and enables shutdown. (Table 3).
Character Registers
The MAX6853 uses 48 character registers (48/1 mode)
(Table 4) or 96 character registers (96/2 mode) (Table
5) to store the 5 x 7 characters (Table 6). Each digit is
represented by 1 byte of memory. The data in the char-
acter registers does not control the character segments
directly. Instead, the register data is used to address a
character generator, which stores the data of the 128-
character font (Table 9). The lower 7 bits of the charac-
ter data (D6 to D0) select a character from the font
table. The most significant bit (MSB) of the register data
(D7) controls the DP segment of the digit; it is set to
light the DP, cleared to leave it unlit.
The character registers address maps are shown in
Table 4 (48/1 mode) and Table 5 (96/2 mode).
In 48/1 mode, the character registers use a single
address range 0x20 to {0x20 + g}, where g is the value
in the grids register (Table 25). The 48/1 mode upper
address limit, when g is 0x2F, is therefore 0x4F. The
address range 0x50 to 0x7F is used for annunciator
data in 48/1 mode.
In 96/2 mode, the character registers use two address
ranges. The first row’s address range is 0x20 to
{0x20 + g}. The second row’s address range is 0x50 to
{0x50 + g}. Therefore, in 96/2 mode, the character regis-
ters are only one contiguous memory range when a 48-
grid display is used.
DISPLAY
MODE
MAXIMUM NO. OF DIGITS
MAXIMUM NO. OF
ANNUNCIATORS
MAXIMUM NO.
OF GRIDS
DIGITS COVERED
BY EACH GRID
48/1 mode
48 digits, each with a DP segment and a cursor
segment
4 per digit
1 digit per grid
96/2 mode
96 digits, each with a DP segment and a cursor
segment
None
48 grids
2 digits per grid
Table 1. Display Modes
COMMAND ADDRESS
REGISTER
D15
D14
D13
D12
D11
D10
D9
D8
HEX
CODE
No-op
R/W
000
0000
0x00
VFBLANK polarity
R/W
000
0001
0x01
Intensity
R/W
000
0010
0x02
Grids
R/W
000
0011
0x03
Configuration
R/W
000
0100
0x04
User-defined fonts
R/W
000
0101
0x05
Output map
R/W
000
0110
0x06
Display test and device ID
R/W
000
0111
0x07
PUMP register
R/W
000
1000
0x08
Filament duty cycle
R/W
000
1001
0x09
PHASE1
R/W
000
1010
0x0A
PHASE2
R/W
000
1011
0x0B
PORT0
R/W
000
1100
0x0C
PORT1
R/W
000
1101
0x0D
Shift limit
R/W
000
1110
0x0E
Cursor
R/W
000
1111
0x0F
Factory reserved. Do not write to register.
X
001
0000
0x10
Table 2. Register Address Map
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