參數(shù)資料
型號: MAX5937LCESA+
廠商: Maxim Integrated
文件頁數(shù): 15/23頁
文件大?。?/td> 382K
描述: IC HOT-SWAP CTRLR -48V 8-SOIC
產品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 100
類型: 熱交換控制器
應用: 通用
內部開關:
電源電壓: -10 V ~ -80 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
供應商設備封裝: 8-SOIC
包裝: 管件
-48V Hot-Swap Controllers with V
IN
Step Immunity and No R
SENSE
______________________________________________________________________________________   15
The margin of V
OUT
with respect to V
SC
and V
CB
was set
when V
SC
and V
CB
were selected from the three avail-
able ranges. This margin may be lower at one of the tem-
perature extremes and if so, that value should be used in
the following discussion. These margins will be called
V
CB
and V
SC
and they represent the minimum V
OUT
excursion required to trip the respective fault.
To set ?/DIV>
STEP
to block all V
CB
and V
SC
faults for any
ramp rate, find the ratio of V
STEP_MON
to V
CB
and
choose ?/DIV>
STEP
so:
?/DIV>
STEP
= 1.2 x ?/DIV>
C
x V
STEP_MON
/ V
CB
And since R
STEP_MON
= 100k&. This results in
C
STEP_MON
= ?/DIV>
STEP
/ 100k&.
After the first-pass component selection, if sufficient
timing margin exists (see Appendix B), it is possible but
not necessary to lower R
STEP_MON
below 100k& to
reduce the sensitivity of STEP_MON to V
IN
noise.
Appendix B gives a more complete analysis and dis-
cussion of the step monitor function. It provides meth-
ods for the characterization of the load response to a
V
IN
ramp and graphical verification of the step monitor
timing margins for a set of design parameters.
Selecting the PGOOD (PGOOD)
Pullup Resistor
Due to the open-drain driver, PGOOD (PGOOD) requires
an external pullup resistor to GND. This resistor should be
selected to minimize the current load while PGOOD
(PGOOD) is low. The PGOOD output specification for V
OL
is 0.4V at 1mA. As described in the Detailed Description,
the external pullup interferes with the ability of PGOOD
(PGOOD) to follow positive V
IN
steps as well as if it were
driven by an active pullup. When PGOOD (PGOOD) is
asserted high, an apparent negative glitch appears at
PGOOD during a positive V
IN
step. To minimize this
negative transient it may be necessary to increase the
pullup current and/or to add a small amount of capaci-
tance from PGOOD (PGOOD) to GND to compensate for
the pin capacitance.
Setting the Test Current Level for
Load-Probe Test
The load-probe test is a current test of the load that
avoids turning on the power MOSFET. The MAX5936/
MAX5937 have an internal switch (Q1 in Figure 14) that
pulls current through the load and through an external
current-limiting resistor, R
LP
. During the test, this switch is
pulsed on for up to 220ms (typ). Current is pulled through
the load, which should charge up the load capacitance
unless there is a short. If the voltage across the load
exceeds 200mV, the test is truncated and normal power-
up is allowed to proceed. If the voltage across the load
does not reach 200mV in the 220ms period that the
current is on, the load is assumed to be shorted and the
current to the load from the LP pin is shut off. The
MAX5936A_/MAX5937A_ time out for 16 x t
LP
then retry
the load-probe test. The MAX5936L_/MAX5937L_ latch
the fault condition indefinitely until the UVLO is brought
below 1.125V for 1.5ms or the power is recycled.
In the application, the current-limiting resistor should be
selected to minimize the current pulled through the load
while guaranteeing that it charges the maximum expected
load capacitance to 220mV in 80ms. These parameters
are the maximum load-probe test voltage and the mini-
mum load-probe current pulse period, respectively. The
maximum current possible is 1A, which is adequate to test
a load capacitance as large as 170,000礔 over the typical
telecom operating voltage range.
I
TEST
(A) = C
LOAD,MAX
(F) x 220mV / 80ms
Since the minimum intended V
IN
for the application
results in the lowest I
TEST
, during the load-probe test,
this V
IN,MIN
should be used to set the R
LP
. This voltage
will likely be near V
ON,FALLING
or V
OFF
for the applica-
tion.
R
TEST
(&) = V
IN,MIN
/ I
TEST
= V
IN,MIN
x 80ms /
(C
LOAD(MAX)
x 220mV)
Example: V
IN
operating range = 36V to 72V, C
LOAD
=
10,000礔. First, find the R
TEST,
which will guarantee a
successful test of the load.
R
LP
= 36V x 80ms / (10,000礔 x 220mV) = 1,309& ?/DIV>
1.30k& ?%
Next, evaluate the R
LP
at the maximum operating volt-
age to verify that it will not exceed the 1A current limit
for the load-probe test:
I
TEST,MAX
= V
IN,MAX
/ R
LP
= 72V / 1.30k& = 55.4mA
If the C
LOAD(MAX)
is increased to 170,000礔, the test
current will approach the limit. In this case, R
TEST
will
be a much lower value and must include the internal
switch resistance. To find the external series resistor
value that will guarantee a successful test at the lowest
supply voltage, the maximum value for the load-probe
switch on-resistance of 11& should be used:
R
LP,TOT
= 36V x 80ms / (170,000礔 x 220mV)
= 77& = 11& + R
LP
R
LP
= 77& - 11& = 66& ?66.5& ?%
Again R
LP
must be evaluated at the maximum operat-
ing voltage to verify that it will not exceed the 1A cur-
rent limit for the load-probe test. In this case, the
minimum value for the load-probe switch on-resistance
of 6& should be used:
I
TEST,MAX
= V
IN,MAX
/ R
LP,TOT
= 72V / (66.5& + 6&)
= 993mA
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