參數(shù)資料
型號： MAX5895EGK+TD
廠商： Maxim Integrated Products
文件頁數(shù)： 7/31頁
文件大小： 0K
描述： IC DAC DUAL 16BIT 500MSPS 68-QFN
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 2,500
設(shè)置時間： 11ns
位數(shù)： 16
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 2
電壓電源： 模擬和數(shù)字
功率耗散（最大）： 511mW
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 68-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 68-QFN 裸露焊盤（10x10）
包裝： 帶卷 (TR)
輸出數(shù)目和類型： 2 電流，單極
采樣率（每秒）： 500M
MAX5895
Programming Registers
Programming its registers with the SPI serial interface
sets the MAX5895 operation modes. Table 2 shows all
of the registers. The following are descriptions of each
register.
16-Bit, 500Msps Interpolating and Modulating
Dual DAC with CMOS Inputs
______________________________________________________________________________________
15
ADD
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
00h
Unused
0 = MSB first
1 = LSB first
Software Reset
0 = Normal
1 = Reset all
registers
Interpolator
Power-Down
0 = Normal
1 = Power-down
IDAC Power-
Down
0 = Normal
1 = Power-down
QDAC Power-
Down
0 = Normal
1 = Power-down
Unused
01h
Interpolation Rate
(Bit 7, Bit 6)
00 = No interpolation
01 = 2x interpolation
10 = 4x interpolation
11 = 8x interpolation
Third
Interpolation
Filter
Configuration
0 = Lowpass
1 = Highpass
Modulation Mode
(Bit 4, Bit 3)
00 = Modulation off
01 = fIM/2
10 = fIM/4
11 = fIM/4
Mixer Modulation
Mode
0 = Complex
1 = Real
Modulation
Sign
0 = e
-j
ω
1 = e
+j
ω
Unused
02h
0 = Two’s
complement
input data
1 = Offset
binary input
data
0 = Single
port (A),
interleaved
I/Q
1 = Dual port
I/Q input
0 = Clock output
on DATACLK
1 = Clock output
on DATA CLK/B14
0 = Input data
latched on
rising clock
edge
1 = Input data
latched on falling
clock edge
0 = Data clock
input enabled
1 = Data clock
output enabled
Data
Synchronizer
0 = Enabled
1 = Disabled
Unused
03h
Unused
04h
8-Bit IDAC Fine-Gain Adjustment (see the Gain Adjustment section). Bit 7 is MSB and bit 0 is LSB. Default: 00h
05h
Unused
4-Bit IDAC Coarse-Gain Adjustment (see the Gain Adjustment
section). Bit 3 is MSB and bit 0 is LSB. Default: Fh
06h
10-Bit IDAC Offset Adjustment (see the Offset Adjustment section). Bits 7 to 0 of the 06h register are the MSB bits. Bit 1 and bit 0 are the LSB
bits in 07h register. Default: 000h
07h
IDAC IOFFSET
Direction
0 = Current on
OUTIN
1 = Current on
OUTIP
Unused
IDAC Offset
Adjustment
Bit 1
(see 06h
register)
IDAC Offset
Adjustment
Bit 0
(see 06h
register)
08h
8-Bit QDAC Fine-Gain Adjustment (see the Gain Adjustment section). Bit 7 is MSB and bit 0 is LSB. Default: 00h
09h
Unused
4-Bit QDAC Coarse-Gain Adjustment (see the Gain Adjustment
section). Bit 3 is MSB and bit 0 is LSB. Default: Fh
0Ah
10-Bit QDAC Offset Adjustment (see the Offset Adjustment section). Bits 7 to 0 of the 0Ah register are the MSB bits. Bit 1 and bit 0 are the
LSB bits in 0Bh register. Default: 000h
0Bh
QDAC
IOFFSET
Direction
0 = Current on
OUTQN
1 = Current on
OUTQP
Unused
QDAC Offset
Adjustment
Bit 1
(see 0Ah
register)
QDAC Offset
Adjustment
Bit 0
(see 0Ah
register)
0Ch
Reserved, do not write to these bits.
0Dh
Reserved, do not write to these bits.
0Eh
Reserved, do not write to these bits.
Table 2. MAX5895 Programmable Registers
Conditions in bold are default states after reset.
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