參數(shù)資料
型號(hào)： MAX5895EGK+TD
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 2/31頁(yè)
文件大?。?/td> 0K
描述： IC DAC DUAL 16BIT 500MSPS 68-QFN
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 2,500
設(shè)置時(shí)間： 11ns
位數(shù)： 16
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 2
電壓電源： 模擬和數(shù)字
功率耗散（最大）： 511mW
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 68-VFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 68-QFN 裸露焊盤(pán)（10x10）
包裝： 帶卷 (TR)
輸出數(shù)目和類(lèi)型： 2 電流，單極
采樣率（每秒）： 500M
MAX5895
16-Bit, 500Msps Interpolating and Modulating
Dual DAC with CMOS Inputs
10
______________________________________________________________________________________
Pin Description
PIN
NAME
FUNCTION
1
CLKP
Noninverting Differential Clock Input
2
CLKN
Inverting Differential Clock Input
3, 4, 5
N.C.
Internally Connected. Do not connect.
6, 21, 30, 37
DVDD1.8
Digital Power Supply. Accepts a 1.71V to 1.89V supply range. Bypass each pin to ground with a
0.1F capacitor as close to the pin as possible.
7–12, 15–20,
22–25
A15–A0
A-Port Data Inputs.
Dual-port mode:
I-channel data input. Data is latched on the rising/falling edge (programmable) of the DATACLK.
Single-port mode:
I-channel and Q-channel data input, with SELIQ.
13, 44
DVDD3.3
CMOS I/O Power Supply. Accepts a 3.0V to 3.6V supply range. Bypass each pin to ground with a
0.1F capacitor as close to the pin as possible.
14
DATACLK
Programmable Data Clock Input/Output. See the DATACLK Modes section for details.
26
SELIQ/B15
Select I/Q-Channel Input or B-Port MSB Input.
Single-port mode:
If SELIQ = LOW, data is latched into Q-channel on the rising/falling edge (programmable) of
the DATACLK.
If SELIQ = HIGH, data is latched into I-channel on the rising/falling edge (programmable) of the
DATACLK.
Dual-port mode:
Q-channel MSB input.
27
DATACLK/B14
Alternate DATACLK Input/Output or B-Port Bit 14 Input.
Single-port mode:
See the DATACLK Modes section for details.
Dual-port mode:
Q-channel bit 14 input.
If unused connect to GND.
28, 29, 31–36,
38–43
B13–B0
B-Port Data Bits 13–0.
Dual-port mode:
Q-channel inputs. Data is latched on the rising/falling (programmable) edge of the DATACLK.
Single-port mode:
Connect to GND.
45
SDO
Serial-Port Data Output
46
SDI
Serial-Port Data Input
47
SCLK
Serial-Port Clock Input. Data on SDI is latched on the rising edge of SCLK.
48
CS
Serial-Port Interface Select. Drive CS low to enable serial-port interface.
49
RESET
Reset Input. Set RESET low during power-up.
50
REFIO
Reference Input/Output. Bypass to ground with a 1F capacitor as close to the pin as possible.
51
DACREF
Current-Set Resistor Return Path. For a 20mA full-scale output current, connect a 2k
resistor
between FSADJ and DACREF. Internally connected to GND. Do not use as an external ground
connection.
52
FSADJ
Full-Scale Adjust Input. This input sets the full-scale output current of the DAC. For a 20mA full-
scale output current, connect a 2k
resistor between FSADJ and DACREF.
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