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參數(shù)資料
| 型號： | MAX5877EGK+TD |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 4/19頁 |
| 文件大小： | 0K |
| 描述： | IC DAC 14BIT DUAL 250MSPS 68-QFN |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 設(shè)置時間： | 14ns |
| 位數(shù)： | 14 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 電壓電源： | 模擬和數(shù)字 |
| 功率耗散（最大）： | 331mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 68-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 68-QFN 裸露焊盤（10x10） |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 4 電流，單極 |
| 采樣率（每秒）： | 250M |
MAX5877
14-Bit, 250Msps, High-Dynamic-Performance,
Dual DAC with LVDS Inputs
12
______________________________________________________________________________________
The MAX5877’s reference circuit (Figure 2) employs a
control amplifier to regulate the full-scale current
IOUTFS for the differential current outputs of the DAC.
Calculate the full-scale output current as follows:
where IOUTFS is the full-scale output current of the
DAC. RSET (located between FSADJ and DACREF)
determines the amplifier’s full-scale output current for
the DAC. See Table 1 for a matrix of different IOUTFS
and RSET selections.
Analog Outputs (OUTIP, OUTIN, OUTQP,
OUTQN)
Each MAX5877 DAC outputs two complementary cur-
rents (OUTIP/N, OUTQP/N) that operate in a single-
ended or differential configuration. A load resistor
converts these two output currents into complementary
single-ended output voltages. A transformer or a differ-
ential amplifier configuration converts the differential
voltage existing between OUTIP (OUTQP) and OUTIN
(OUTQN) to a single-ended voltage. If not using a
transformer, the recommended termination from the
output is a 25
termination resistor to ground and a
50
resistor between the outputs.
To generate a single-ended output, select OUTIP (or
OUTQP) as the output and connect OUTIN (or OUTQN)
to GND. SFDR degrades with single-ended operation
or increased output swing. Figure 3 displays a simpli-
fied diagram of the internal output structure of the
MAX5877.
Clock Inputs (CLKP, CLKN)
The MAX5877 features flexible differential clock inputs
(CLKP, CLKN) operating from a separate supply
(AVCLK) to achieve optimum jitter performance. Drive
the differential clock inputs from a single-ended or a
differential clock source. For single-ended operation,
drive CLKP with a logic source and bypass CLKN to
GND with a 0.1F capacitor.
CLKP and CLKN are internally biased to AVCLK / 2. This
facilitates the AC-coupling of clock sources directly to
the device without external resistors to define the DC
level. The dynamic input resistance from CLKP and
CLKN to ground is 5k
.
I
V
R
OUTFS
REFIO
SET
=×
×
32
1
2
14
Table 1. IOUTFS and RSET Selection
Matrix Based on a Typical +1.200V
Reference Voltage
RSET (k
)
FULL-SCALE
CURRENT IOUTFS (mA)
CALCULATED
1% EIA STD
2
19.2
19.1
5
7.68
7.5
10
3.84
3.83
15
2.56
2.55
20
1.92
1.91
OUTIP
OUTIN
+1.2V
REFERENCE
CURRENT-SOURCE
ARRAY DAC
REFIO
FSADJ
RSET
IREF
10k
DACREF
1
F
IREF = VREFIO / RSET
GND
Figure 2. Reference Architecture, Internal Reference
Configuration
IOUT
OUTIN OUTIP
CURRENT
SOURCES
CURRENT
SWITCHES
AVDD
Figure 3. Simplified Analog Output Structure
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