參數(shù)資料
型號： MAX5877EGK+TD
廠商： Maxim Integrated Products
文件頁數(shù)： 14/19頁
文件大?。?/td> 0K
描述： IC DAC 14BIT DUAL 250MSPS 68-QFN
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 2,500
設(shè)置時間： 14ns
位數(shù)： 14
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 2
電壓電源： 模擬和數(shù)字
功率耗散（最大）： 331mW
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 68-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 68-QFN 裸露焊盤（10x10）
包裝： 帶卷 (TR)
輸出數(shù)目和類型： 4 電流，單極
采樣率（每秒）： 250M
MAX5877
14-Bit, 250Msps, High-Dynamic-Performance,
Dual DAC with LVDS Inputs
4
_______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(AVDD3.3 = DVDD3.3 = AVCLK = +3.3V, AVDD1.8 = DVDD1.8 = +1.8V, GND = 0, fCLK = 2 x fDAC, external reference VREFIO = +1.25V, out-
put load 50
double-terminated, transformer-coupled output, IOUTFS = 20mA, TA = TMIN to TMAX, unless otherwise noted. Typical values
are at TA = +25°C.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Reference Input Compliance
Range
VREFIOCR
0.125
1.260
V
Reference Input Resistance
RREFIO
10
k
Reference Voltage Drift
TCOREF
±25
ppm/
°C
ANALOG OUTPUT TIMING (See Figure 4)
Output Fall Time
tFALL
90% to 10% (Note 5)
0.7
ns
Output Rise Time
tRISE
10% to 90% (Note 5)
0.7
ns
Output-Voltage Settling Time
tSETTLE
Output settles to 0.025% FS (Note 5)
14
ns
Output Propagation Delay
tPD
Excluding data latency (Note 5)
1.1
ns
Glitch Impulse
Measured differentially
1
pVs
IOUTFS = 2mA
30
Output Noise
nOUT
IOUTFS = 20mA
30
pA/
√Hz
TIMING CHARACTERISTICS
Data to Clock Setup Time
tSETUP
Referenced to rising edge of clock (Note 6)
-1.2
ns
Data to Clock Hold Time
tHOLD
Referenced to rising edge of clock (Note 6)
2.0
ns
Latency to I output
9
Data Latency
Latency to Q output
8
Clock
Cycles
Minimum Clock Pulse-Width High
tCH
CLKP, CLKN
0.9
ns
Minimum Clock Pulse-Width Low
tCL
CLKP, CLKN
0.9
ns
LVDS LOGIC INPUTS (B13P/B13N–B0P/B0N, XORN, XORP, SELIQN, SELIQP)
Differential Input-Logic High
VIH
100
mV
Differential Input-Logic Low
VIL
-100
mV
Common-Mode Voltage Range
VCMR
1.125
1.375
V
Differential Input Resistance
RIN
(Note 7)
110
Input Capacitance
CIN
2.5
pF
CMOS LOGIC INPUTS (PD, TORB)
Input-Logic High
VIH
0.7 x
DVDD3.3
V
Input-Logic Low
VIL
0.3 x
DVDD3.3
V
Input Leakage Current
IIN
-20
1
+20
A
PD, TORB Internal Pulldown
Resistance
VPD = VTORB = 3.3V
1.5
M
Input Capacitance
CIN
2.5
pF
CLOCK INPUTS (CLKP, CLKN)
Sine wave
> 1.5
Differential Input
Voltage Swing
Square wave
> 0.5
VP-P
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