參數(shù)資料
型號: MAX5741EUB+T
廠商: Maxim Integrated Products
文件頁數(shù): 9/15頁
文件大?。?/td> 0K
描述: IC DAC 10BIT QUAD LP SER 10-UMAX
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
設(shè)置時間: 4µs
位數(shù): 10
數(shù)據(jù)接口: 串行
轉(zhuǎn)換器數(shù)目: 4
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 10-TFSOP,10-MSOP(0.118",3.00mm 寬)
供應(yīng)商設(shè)備封裝: 10-µMAX
包裝: 帶卷 (TR)
輸出數(shù)目和類型: 4 電壓,單極;4 電壓,雙極
采樣率(每秒): *
MAX5741
10-Bit, Low-Power, Quad, Voltage-Output
DAC with Serial Interface
_______________________________________________________________________________________
3
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +2.7V to +5.5V, GND = 0, VREF = VDD, RL = 5k, CL = 200pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are
VDD = +5V, TA = +25°C.)
TIMING CHARACTERISTICS
(VDD = 2.7V to 5.5V, GND = 0, TA = TMIN to TMAX, unless otherwise noted.)
Note 1: DC specifications are tested without output loads.
Note 2: Linearity guaranteed from code 29 to code 995.
Note 3: Limited with test conditions.
Note 4: Offset and gain error limit the FSR.
Note 5: Guaranteed by design.
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DIGITAL INPUTS (SCLK, DIN,
CS)
Input High Voltage
VIH
VDD = +3V, +5V
0.7
VDD
V
Input Low Voltage
VIL
VDD = +3V, +5V
0.3
VDD
V
Input Leakage Current
IIN
Digital inputs = 0 or VDD
±0.1
±1
A
Input Capacitance
CIN
5pF
DYNAMIC PERFORMANCE
Voltage Output Slew Rate
SR
0.5
V/s
Voltage Output Settling Time
100 hex to 300 hex (Note 3)
4
10
s
Digital Feedthrough
Any digital inputs from 0 to VDD
0.15
nV-s
Digital-Analog Glitch Impulse
Major carry transition (Code 1FF hex to
Code 200 hex)
12
nV-s
DAC-to-DAC Crosstalk
2.4
nV-s
POWER REQUIREMENTS
Supply Voltage Range
VDD
2.7
5.5
V
All digital inputs at 0 or VDD = 3.6V
230
395
Supply Current with No Load
IDD
All digital inputs at 0 or VDD = 5.5V
270
420
A
Power-Down Supply Current
IDDPD
All digital inputs at 0 or VDD = 5.5V
0.29
1
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SCLK Clock Frequency
f SCLK
020
MHz
SCLK Pulse Width High
tCH
25
ns
SCLK Pulse Width Low
tCL
25
ns
CS Fall to SCLK Rise Setup Time
tCSS
10
ns
SCLK Fall to CS Rise Setup Time
tCSH
10
ns
DIN to SCLK Fall Setup Time
tDS
15
ns
DIN to SCLK Fall Hold Time
tDH
0ns
CS Pulse Width High
tCSW
80
ns
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