參數(shù)資料
型號(hào): MAX5741EUB+T
廠商: Maxim Integrated Products
文件頁數(shù): 2/15頁
文件大?。?/td> 0K
描述: IC DAC 10BIT QUAD LP SER 10-UMAX
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
設(shè)置時(shí)間: 4µs
位數(shù): 10
數(shù)據(jù)接口: 串行
轉(zhuǎn)換器數(shù)目: 4
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 10-TFSOP,10-MSOP(0.118",3.00mm 寬)
供應(yīng)商設(shè)備封裝: 10-µMAX
包裝: 帶卷 (TR)
輸出數(shù)目和類型: 4 電壓,單極;4 電壓,雙極
采樣率(每秒): *
MAX5741
10-Bit, Low-Power, Quad, Voltage-Output
DAC with Serial Interface
10
______________________________________________________________________________________
tents to the DAC latch. CS may then either be held low
or brought high. CS must be brought high for a mini-
mum of 80ns before the next write sequence, since a
write sequence is initiated on a falling edge of CS. Not
keeping CS low during the first 15 SCLK cycles dis-
cards input data. The serial clock (SCLK) can idle
either high or low between transitions.
The MAX5741 has two internal registers per DAC, the
input register and the DAC register. The input register
holds the data that is waiting to be shifted to the DAC
register. All four input registers can be loaded without
updating the output. This function is useful when all out-
puts need to be updated at the same time. The input
register can be made transparent. When the input reg-
ister is transparent, the data written into DIN loads
directly to the DAC register and the output is updated.
The DAC output is not updated until data is written to
the DAC register. See Table 2 for a list of serial-inter-
face programming commands.
Power-On Reset (POR)
The MAX5741 has an internal POR circuit. At power-up all
DACs are powered-down and OUT_ is terminated to
GND through 100k resistors. Contents of input and DAC
registers are cleared to all zero. 8s recovery time after
issuing a wake-up command is needed before writing to
the DAC registers. Power-down mode control commands
can be applied immediately with no recovery time.
C3–C0 are control bits. The data bits D9 to D0 are in
straight binary format. Set bits S1 and S0 to zero. All
zeros correspond to zero scale and all ones corre-
spond to full scale.
EXTENDED
CONTROL
DATA BITS
C3
C2
C1
C0
D9–D3
D2
D1
D0
S1
S0
DESCRIPTION
FUNCTION
1
X
0
0000
DAC A
DAC O/P, wake-up
1
X
0
0001
DAC A
Floating output
1
X
0
0010
DAC A
Output is terminated with 1k
1
X
0
0011
DAC A
Output is terminated with 100k
1
X
0
0100
DAC B
DAC O/P, wake-up
1
X
0
0101
DAC B
Floating output
1
X
0
0110
DAC B
Output is terminated with 1k
1
X
0
0111
DAC B
Output is terminated with 100k
1
X
0
1000
DAC C
DAC O/P, wake-up
1
X
0
1001
DAC C
Floating output
1
X
0
1010
DAC C
Output is terminated with 1k
1
X
0
1011
DAC C
Output is terminated with 100k
1
X
0
1100
DAC D
DAC O/P, wake-up
1
X
0
1101
DAC D
Floating output
1
X
0
1110
DAC D
Output is terminated with 1k
1
X
0
1111
DAC D
Output is terminated with 100k
1
X
1
0000
DAC A-D
DAC O/P, wake-up
1
X
1
0001
DAC A-D
Floating output
1
X
1
0010
DAC A-D
Output is terminated with 1k
1
X
1
0011
DAC A-D
Output is terminated with 100k
Table 1. Power-Down Mode Control
X = Don’t Care
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