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參數(shù)資料
| 型號(hào)： | MAX5511ETC+ |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 14/18頁 |
| 文件大小： | 0K |
| 描述： | IC DAC 8BIT VOUT 12-TQFN-EP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 75 |
| 設(shè)置時(shí)間： | 660µs |
| 位數(shù)： | 8 |
| 數(shù)據(jù)接口： | MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 1.35W |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 12-WQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 12-TQFN-EP（4x4） |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 1 電壓，單極；1 電壓，雙極 |
| 采樣率（每秒）： | * |
MAX5510/MAX5511
+1.8V to +5.5V, Ultra-Low-Power, 8-Bit,
Voltage-Output DACs
_______________________________________________________________________________________
5
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
TIMING CHARACTERISTICS (VDD = 4.5V TO 5.5V)
Serial Clock Frequency
fSCLK
0
16.7
MHz
DIN to SCLK Rise Setup Time
tDS
15
ns
DIN to SCLK Rise Hold Time
tDH
0ns
SCLK Pulse-Width High
tCH
24
ns
SCLK Pulse-Width Low
tCL
24
ns
CS Pulse-Width High
tCSW
100
ns
SCLK Rise to CS Rise Hold Time
tCSH
0ns
CS Fall to SCLK Rise Setup Time
tCSS
20
ns
SCLK Fall to CS Fall Setup
tCSO
0ns
CS Rise to SCK Rise Hold Time
tCS1
20
ns
TIMING CHARACTERISTICS
(VDD = +4.5V to +5.5V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
TIMING CHARACTERISTICS
(VDD = +1.8V to +5.5V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
Note 1: Linearity is tested within codes 6 to 255.
Note 2: Offset is tested at code 6.
Note 3: Gain is tested at code 250. FB is connected to OUT.
Note 4: Guaranteed by design. Not production tested.
Note 5: VDD must be a minimum of 1.8V.
Note 6: Outputs can be shorted to VDD or GND indefinitely, provided that the package power dissipation is not exceeded.
Note 7: Optimal noise performance is at 2nF load capacitance.
Note 8: Thermal hysteresis is defined as the change in the initial +25°C output voltage after cycling the device from TMAX to TMIN.
Note 9: All digital inputs at VDD or GND.
Note 10: Load = 10k
in parallel with 100pF, VDD = 5V, VREF = 4.096V (MAX5510) or VREF = 3.9V (MAX5511).
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
TIMING CHARACTERISTICS (VDD = 1.8V TO 5.5V)
Serial Clock Frequency
fSCLK
010
MHz
DIN to SCLK Rise Setup Time
tDS
24
ns
DIN to SCLK Rise Hold Time
tDH
0
ns
SCLK Pulse-Width High
tCH
40
ns
SCLK Pulse-Width Low
tCL
40
ns
CS Pulse-Width High
tCSW
150
ns
SCLK Rise to CS Rise Hold Time
tCSH
0
ns
CS Fall to SCLK Rise Setup Time
tCSS
30
ns
SCLK Fall to CS Fall Setup
tCSO
0
ns
CS Rise to SCK Rise Hold Time
tCS1
30
ns
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