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參數(shù)資料
| 型號(hào)： | MAX5479EUD+T |
| 廠商： | Maxim Integrated Products |
| 文件頁(yè)數(shù)： | 11/16頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC POT DGTL DUAL 256-TAP 14TSSOP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 接片： | 256 |
| 電阻（歐姆）： | 100k |
| 電路數(shù)： | 2 |
| 溫度系數(shù)： | 標(biāo)準(zhǔn)值 70 ppm/°C |
| 存儲(chǔ)器類型： | 非易失 |
| 接口： | I²C（設(shè)備位址） |
| 電源電壓： | 2.7 V ~ 5.25 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 14-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 14-TSSOP |
| 包裝： | 帶卷 (TR) |
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MAX5477/MAX5478/MAX5479
Dual, 256-Tap, Nonvolatile, I2C-Interface,
Digital Potentiometers
4
_______________________________________________________________________________________
Note 2:
All devices are production tested at TA = +25°C and are guaranteed by design and characterization for -40°C < TA < +85°C.
Note 3:
The DNL and INL are measured with the potentiometer configured as a voltage-divider with H_ = VDD and L_ = GND. The
wiper terminal is unloaded and measured with a high-input-impedance voltmeter.
Note 4:
The DNL and INL are measured with the potentiometer configured as a variable resistor. H_ is unconnected and L_ =
GND. For VDD = +5V, the wiper is driven with 400A (MAX5477), 80A (MAX5478), or 40A (MAX5479). For VDD = +3V,
the wiper is driven with 200A (MAX5477), 40A (MAX5478), or 20A (MAX5479).
Note 5:
The wiper resistance is measured using the source currents given in Note 3.
Note 6:
The devices draw current in excess of the specified supply current when the digital inputs are driven with voltages between
(VDD - 0.5V) and (GND + 0.5V). See Supply Current vs. Digital Input Voltage in the Typical Operating Characteristics.
Note 7:
Wiper at midscale with a 10pF load (DC measurement). L_ = GND, an AC source is applied to H_, and the W_ output is
measured. A 3dB bandwidth occurs when the AC W_/H_ value is 3dB lower than the DC W_/H_ value.
Note 8:
The programming current exists only during power-up and EEPROM writes.
Note 9:
The SCL clock period includes rise and fall times (tR = tF). All digital input signals are specified with tR = tF = 2ns and
timed from a voltage level of (VIL + VIH) / 2.
Note 10: Digital timing is guaranteed by design and characterization, and is not production tested.
Note 11: This is measured from the STOP pulse to the time it takes the output to reach 50% of the output step size (divider mode). It
is measured with a maximum external capacitive load of 10pF.
Note 12: An appropriate bus pullup resistance must be selected depending on board capacitance. Refer to the I
2C-bus specifica-
tion document linked to this web address: www.semiconductors.philips.com/acrobat/literature/9398/39340011.pdf
Note 13: The idle time begins from the initiation of the STOP pulse.
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ANALOG SECTION
MAX5477
325
MAX5478
500
Wiper Settling Time (Note 11)
tWS
MAX5479
1000
ns
DIGITAL SECTION
SCL Clock Frequency
fSCL
400
kHz
Setup Time for START Condition
tSU:STA
0.6
s
Hold Time for START Condition
tHD:STA
0.6
s
SCL High Time
tHIGH
0.6
s
SCL Low Time
tLOW
1.3
s
Data Setup Time
tSU:DAT
100
ns
Data Hold Time
tHD:DAT
0
0.9
s
SDA, SCL Rise Time
tR
300
ns
SDA, SCL Fall Time
tF
300
ns
Setup Time for STOP Condition
tSU:STO
0.6
s
Bus Free Time Between STOP and
START Condition
tBUF
Minimum power-up rate = 0.2V/s
1.3
s
Pulse Width of Spike Suppressed
tSP
50
ns
Capacitive Load for Each Bus Line
CB
(Note 12)
400
pF
Write NV Register Busy Time
(Note 13)
12
ms
TIMING CHARACTERISTICS
(VDD = +2.7V to +5.25V, H_ = VDD, L_ = GND, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VDD = +5V,
TA = +25°C. See Figure 1.) (Notes 9 and 10)
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