- 鎮ㄧ従(xi脿n)鍦ㄧ殑浣嶇疆锛�璨疯常IC缍�(w菐ng) > PDF鐩寗10764 > MAX537BCWE (Maxim Integrated Products)IC DAC QUAD CALBRTD 12BIT 16SOIC PDF璩囨枡涓嬭級
鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉(h脿o)锛� | MAX537BCWE |
| 寤犲晢锛� | Maxim Integrated Products |
| 鏂囦欢闋佹暩(sh霉)锛� | 8/24闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC DAC QUAD CALBRTD 12BIT 16SOIC |
| 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 46 |
| 瑷�(sh猫)缃檪(sh铆)闁擄細 | 3µs |
| 浣嶆暩(sh霉)锛� | 12 |
| 鏁�(sh霉)鎿�(j霉)鎺ュ彛锛� | 涓茶 |
| 杞�(zhu菐n)鎻涘櫒鏁�(sh霉)鐩細 | 4 |
| 闆诲闆绘簮锛� | 闆� ± |
| 鍔熺巼鑰楁暎锛堟渶澶э級锛� | 762mW |
| 宸ヤ綔婧害锛� | 0°C ~ 70°C |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 16-SOIC锛�0.295"锛�7.50mm 瀵級 |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 16-SOIC W |
| 鍖呰锛� | 绠′欢 |
| 杓稿嚭鏁�(sh霉)鐩拰椤炲瀷锛� | 4 闆诲锛屽柈妤�锛�4 闆诲锛岄洐妤� |
| 閲囨ǎ鐜囷紙姣忕锛夛細 | * |
绗�1闋�绗�2闋�绗�3闋�绗�4闋�绗�5闋�绗�6闋�绗�7闋�鐣�(d膩ng)鍓嶇8闋�绗�9闋�绗�10闋�绗�11闋�绗�12闋�绗�13闋�绗�14闋�绗�15闋�绗�16闋�绗�17闋�绗�18闋�绗�19闋�绗�20闋�绗�21闋�绗�22闋�绗�23闋�绗�24闋�
MAX536/MAX537
When daisy-chaining MAX536s, the delay from CS
low to SCK high (tCSS) must be the greater of:
tDV + tDS
or
tTR + tRC + tDS - tCSW
where tRC is the time constant of the external pullup resistor
(Rp) and the load capacitance (C) at SDO. For tRC < 20ns,
tCSS is simply tDV + tDS. Calculate tRC from the following
equation:
tRC = Rp (C)
ln
where VPULLUP is the voltage to which the pullup resistor is
connected.
Additionally, when daisy-chaining devices, the maximum
clock frequency is limited to:
1
fSCK(max) = 鈥斺€斺€斺€斺€斺€斺€斺€斺€斺€斺€斺€斺€斺€�
2 (tDO + tRC - 38ns + tDS)
For example, with tRC = 23ns (5V 卤10% supply with
Rp = 1k
and C = 30pF), the maximum clock frequency is
8.7MHz.
Figure 9 shows an alternate method of connecting several
MAX536/MAX537s. In this configuration, the data bus is
common to all devices; data is not shifted through a
daisy-chain. More I/O lines are required in this configu-
ration because a dedicated chip-select input (CS) is
required for each IC.
Calibrated, Quad, 12-Bit
Voltage-Output DACs with Serial Interface
16
______________________________________________________________________________________
VPULLUP
VPULLUP - 2.4V
Table 1. Serial-Interface Programming Commands
鈥淴鈥� = Don鈥檛 Care. LDAC provides true latch control: when LDAC is low, the DAC registers are transparent; when LDAC is high,
the DAC registers are latched.
Mode 0, DOUT clocked out on SCK鈥檚 falling edge. All DACs
updated from their respective input registers.
Mode 1 (default condition at power-up), DOUT clocked out on
SCK鈥檚 rising edge. All DACs updated from their respective
input registers.
Load DAC D input register; DAC D is immediately updated.
0
12-bit DAC data
1
X
1
Load DAC C input register; DAC C is immediately updated.
0
12-bit DAC data
1
X
0
1
Load DAC B input register; DAC B is immediately updated.
0
12-bit DAC data
1
X
1
0
Load DAC A input register; DAC A is immediately updated.
0
12-bit DAC data
1
0
X
0
X
XXXXXXXXXXXX
0
1
0
1
X
XXXXXXXXXXXX
0
1
Update all DACs from their respective input registers.
1
XXXXXXXXXXXX
0
1
X
0
No operation (NOP)
X
XXXXXXXXXXXX
0
1
X
Load all DACs from shift register.
X
12-bit DAC data
0
X
Load input register D; all DAC registers updated.
1
12-bit DAC data
1
Load input register C; all DAC registers updated.
1
12-bit DAC data
1
0
1
Load input register B; all DAC registers updated.
1
12-bit DAC data
1
0
Load input register A; all DAC registers updated.
1
12-bit DAC data
1
0
Load DAC D input register; DAC output unchanged.
1
12-bit DAC data
1
0
1
Load DAC C input register; DAC output unchanged.
1
12-bit DAC data
1
0
1
Load DAC B input register; DAC output unchanged.
1
12-bit DAC data
1
0
1
0
Load DAC A input register; DAC output unchanged.
1
12-bit DAC data
1
0
D11鈥0
C0
C1
A0
A1
FUNCTION
LDAC
16-BIT SERIAL WORD
()
[
]
鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
|---|---|
| MAX537BCPE | IC DAC QUAD CALBRTD 12BIT 16-DIP |
| MAX537ACWE | IC DAC QUAD CALBRTD 12BIT 16SOIC |
| MAX536ACPE | IC DAC QUAD CALBRTD 12BIT 16-DIP |
| VI-J6L-MW-F1 | CONVERTER MOD DC/DC 28V 100W |
| MAX5355EUA | IC DAC 3.3V V-OUT 10BIT 8-UMAX |
鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| MAX537BCWE+ | 鍔熻兘鎻忚堪:鏁�(sh霉)妯¤綁(zhu菐n)鎻涘櫒- DAC 12-Bit 4Ch Precision DAC RoHS:鍚� 鍒堕€犲晢:Texas Instruments 杞�(zhu菐n)鎻涘櫒鏁�(sh霉)閲�:1 DAC 杓稿嚭绔暩(sh霉)閲�:1 杞�(zhu菐n)鎻涢€熺巼:2 MSPs 鍒嗚鲸鐜�:16 bit 鎺ュ彛椤炲瀷:QSPI, SPI, Serial (3-Wire, Microwire) 绌�(w臎n)瀹氭檪(sh铆)闁�:1 us 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:SOIC-14 灏佽:Tube |
| MAX537BCWE+T | 鍔熻兘鎻忚堪:鏁�(sh霉)妯¤綁(zhu菐n)鎻涘櫒- DAC 12-Bit 4Ch Precision DAC RoHS:鍚� 鍒堕€犲晢:Texas Instruments 杞�(zhu菐n)鎻涘櫒鏁�(sh霉)閲�:1 DAC 杓稿嚭绔暩(sh霉)閲�:1 杞�(zhu菐n)鎻涢€熺巼:2 MSPs 鍒嗚鲸鐜�:16 bit 鎺ュ彛椤炲瀷:QSPI, SPI, Serial (3-Wire, Microwire) 绌�(w臎n)瀹氭檪(sh铆)闁�:1 us 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:SOIC-14 灏佽:Tube |
| MAX537BCWE-T | 鍔熻兘鎻忚堪:鏁�(sh霉)妯¤綁(zhu菐n)鎻涘櫒- DAC RoHS:鍚� 鍒堕€犲晢:Texas Instruments 杞�(zhu菐n)鎻涘櫒鏁�(sh霉)閲�:1 DAC 杓稿嚭绔暩(sh霉)閲�:1 杞�(zhu菐n)鎻涢€熺巼:2 MSPs 鍒嗚鲸鐜�:16 bit 鎺ュ彛椤炲瀷:QSPI, SPI, Serial (3-Wire, Microwire) 绌�(w臎n)瀹氭檪(sh铆)闁�:1 us 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:SOIC-14 灏佽:Tube |
| MAX537BEPE | 鍔熻兘鎻忚堪:鏁�(sh霉)妯¤綁(zhu菐n)鎻涘櫒- DAC RoHS:鍚� 鍒堕€犲晢:Texas Instruments 杞�(zhu菐n)鎻涘櫒鏁�(sh霉)閲�:1 DAC 杓稿嚭绔暩(sh霉)閲�:1 杞�(zhu菐n)鎻涢€熺巼:2 MSPs 鍒嗚鲸鐜�:16 bit 鎺ュ彛椤炲瀷:QSPI, SPI, Serial (3-Wire, Microwire) 绌�(w臎n)瀹氭檪(sh铆)闁�:1 us 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:SOIC-14 灏佽:Tube |
| MAX537BEPE+ | 鍔熻兘鎻忚堪:鏁�(sh霉)妯¤綁(zhu菐n)鎻涘櫒- DAC 12-Bit 4Ch Precision DAC RoHS:鍚� 鍒堕€犲晢:Texas Instruments 杞�(zhu菐n)鎻涘櫒鏁�(sh霉)閲�:1 DAC 杓稿嚭绔暩(sh霉)閲�:1 杞�(zhu菐n)鎻涢€熺巼:2 MSPs 鍒嗚鲸鐜�:16 bit 鎺ュ彛椤炲瀷:QSPI, SPI, Serial (3-Wire, Microwire) 绌�(w臎n)瀹氭檪(sh铆)闁�:1 us 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:SOIC-14 灏佽:Tube |
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