參數(shù)資料
型號： MAX5195EGM
廠商： MAXIM INTEGRATED PRODUCTS INC
元件分類： DAC
英文描述： 14-Bit, 260Msps High-Dynamic Performance DAC
中文描述： PARALLEL, WORD INPUT LOADING, 14-BIT DAC, QCC48
封裝： 7 X 7 MM, 0.90 MM HEIGHT, QFN-48
文件頁數(shù)： 4/17頁
文件大小： 599K
代理商： MAX5195EGM
Note 1:
Offset error is the deviation of the output voltage from its ideal value at midscale.
Note 2:
Full-scale gain error is the deviation of the output voltage from the ideal full-scale value. The actual full-scale voltage is
determined by V
OUTP
- V
OUTN
, when D0P
–
D13P are set high and D0N
–
D13N are set low.
Note 3:
Propagation delay is the time difference between the active edge of the clock and the active edge of the output.
Note 4:
Power-supply rejection ratio is the full-scale output change as the supply voltage varies over its specified range.
M
14-Bit, 260Msps High-Dynamic
Performance DAC
4
_______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(AV
CC
= DV
CC
= 5V, AGND = DGND = 0, external reference V
REFIN
= 1.196V, R
T
= 27.4
referenced to AV
CC
, V
OUT
= 1V
P-P
,
R
SET
= 3.83k
, f
CLK
= 156MHz, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25
°
C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ANALOG OUTPUT TIMING
Output Fall Time
Output Rise Time
Glitch Energy
TIMING CHARACTERISTICS
t
FALL
t
RISE
90% to 10%
10% to 90%
0.8
0.8
0.5
ns
ns
pV-s
Data-to-Clock Setup Time
(D0N
–
D13N, D0P
–
D13P)
t
SETUP
Referenced to the rising edge, Figure 4
0.5
1
ns
Data-to-Clock Hold Time
(D0N
–
D13N, D0P
–
D13P)
t
HOLD
Referenced to the rising edge, Figure 4
0.5
1.1
ns
Propagation Delay Time
Minimum Clock Pulse Width High
Minimum Clock Pulse Width Low
LOGIC INPUTS (D0N–D13N, D0P–D13P, CLKP, CLKN)
Input Logic High
Input Logic Low
Input Logic Current, Logic High
Input Logic Current, Logic Low
Digital Input Capacitance
POWER SUPPLIES
Analog Supply Voltage Range
Digital Supply Voltage Range
Analog Supply Current
Digital Supply Current
Power Dissipation
Power-Supply Rejection Ratio
t
PD
t
CH
t
CL
(Note 3)
CLKP, CLKN
CLKP, CLKN
0.5
ns
ns
ns
1.6
1.6
V
IH
V
IL
I
IH
I
IL
C
IN
2.4
V
V
μA
μA
pF
1.6
+300
+300
V
IH
= 2.4V
V
IL
= 1.6V
-300
-300
50
10
2
AV
CC
DV
CC
I
AVCC
I
DVCC
P
DISS
PSRR
4.75
4.75
5
5
48
190
1190
0.2
5.25
5.25
58
230
1440
V
V
AV
CC
= DV
CC
= 5V
AV
CC
= DV
CC
= 5V
AV
CC
= DV
CC
= 5V
AV
CC
= DV
CC
= 5V
±
5% (Note 4)
mA
mA
mW
%FS/V
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