參數(shù)資料
型號: MAX5195EGM
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: DAC
英文描述: 14-Bit, 260Msps High-Dynamic Performance DAC
中文描述: PARALLEL, WORD INPUT LOADING, 14-BIT DAC, QCC48
封裝: 7 X 7 MM, 0.90 MM HEIGHT, QFN-48
文件頁數(shù): 11/17頁
文件大?。?/td> 599K
代理商: MAX5195EGM
LVPECL-Compatible Digital Inputs
(D0P–D13P, D0N–D13N)
The MAX5195 digital interface consists of 14 differen-
tial, LVPECL-compatible digital input pins. These inputs
follow standard positive binary coding where D0P and
D0N represent the differential inputs to the least signifi-
cant bit (LSB), and D13P and D13N represent the dif-
ferential pair associated with the most significant bit
(MSB). D0P/N through D13P/N accept LVPECL input
levels of 0.8V
P-P
(Table 2).
Each of the digital input terminals can be terminated
with a separate 50
resistor; however, to achieve the
lowest noise performance, it is recommended to termi-
nate each differential pair with a 100
resistor located
between the positive and negative input terminals.
Clock Inputs (CLKP, CLKN) and Data
Timing Relationship
The MAX5195 features differential, LVPECL-compatible
clock inputs. Internal edge-triggered flip-flops latch the
input word on the rising edge of the clock-input pair
CLKP/CLKN. The DAC is updated with the data word
on the next rising edge of the clock input. This results in
a conversion latency of one clock cycle. The MAX5195
provides for minimum setup and hold times (<2ns), allow-
ing for noncritical external interface timing (Figure 4).
For best AC performance, a differential, DC-coupled
clock signal with LVPECL-compatible voltage levels
(Table 2) should be used. The MAX5195 operates
properly with a clock duty cycle set within the limits list-
ed in the
Electrical Characteristics
table. However, a
50% duty cycle should be utilized for optimum dynamic
performance. To maintain the DAC
s excellent dynamic
performance, clock and data signals should originate
from separate signal sources.
Analog Outputs (OUTP, OUTN)
The MAX5195
s current array is designed to drive full-
scale currents of 10mA to 20mA into an internal R2R
resistor network (R
R2R
). To achieve the desired differ-
ential output voltage range of 0.5V
P-P
to 1V
P-P
, both
OUTP and OUTN should be externally terminated into
27.4
(R
T
), resulting in a combined load of R
LOAD
=
25
(Figure 5):
R
LOAD
= R
R2R
|| R
T
R
LOAD
= (285
27.4
) / (285
+ 27.4
)
R
LOAD
= 25
M
14-Bit, 260Msps High-Dynamic
Performance DAC
______________________________________________________________________________________
11
PARAMETER
MINIMUM LVPECL SPECIFICATION
V
CC
** - 1.16V
V
CC
** - 1.81V
MAXIMUM LVPECL SPECIFICATION
V
CC
** - 0.88V
V
CC
** - 1.48V
V
CC
** - 1.3V
Input Voltage High
Input Voltage Low
Common-Mode Level
**
V
CC
is the supply voltage associated with the LVPECL source. A typical V
CC
level associated with LVPECL is 3.3V, which sets the
common-mode level to 2V, allowing a typical peak-to-peak signal swing of 0.8V.
Table 2. LVPECL Voltage Levels
CLKP
CLKN
D13
D0
OUTP
OUTN
10% POINT
90% POINT
t
CH
t
SETUP
t
HOLD
t
PD
t
CL
t
RISE
, t
FALL
MAX5195
Figure 4. Input/Output Timing Information
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