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參數(shù)資料
| 型號： | MAX5189BEEI+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 5/14頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 8BIT DUAL 40MHZ 28-QSOP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 設(shè)置時(shí)間： | 25µs |
| 位數(shù)： | 8 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SSOP（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-QSOP |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 4 電壓，單極 |
| 采樣率（每秒）： | * |
MAX5186/MAX5189
Dual, 8-Bit, 40MHz, Current/Voltage,
Simultaneous-Output DACs
______________________________________________________________________________________
13
BP
FILTER
DAC2
CARRIER
FREQUENCY
MAX2452
IF
Q COMPONENT
BP
FILTER
3V
DIGITAL
SIGNAL
PROCESSOR
QUADRATURE
MODULATOR
I COMPONENT
0
°
90
°
Σ
3V
MAX5186
MAX5189
DAC1
Figure 6. Using the MAX5186/MAX5189 for I/Q Signal Reconstruction
Grounding and Power-Supply Decoupling
Grounding and power-supply decoupling strongly influ-
ence the MAX5186/MAX5189’s performance. Unwanted
digital crosstalk may couple through the input, refer-
ence, power-supply, and ground connections, which
may affect dynamic specifications like signal-to-noise
ratio or SFDR. In addition, electromagnetic interference
(EMI) can either couple into or be generated by the
MAX5186/MAX5189. Therefore, grounding and power-
supply decoupling guidelines for high-speed, high-fre-
quency applications should be closely followed.
First, a multilayer printed circuit (PC) board with sepa-
rate ground and power-supply planes is recommend-
ed. High-speed signals should be run on controlled
impedance lines directly above the ground plane.
Since the MAX5186/MAX5189 have separate analog
and digital ground buses (AGND and DGND, respec-
tively), the PC board should also have separate analog
and digital ground sections with only one point con-
necting the two. Digital signals should run above the
digital ground plane, and analog signals should run
above the analog ground plane. Digital signals should
be kept far away from the sensitive analog reference
and clock input.
Both devices have two power-supply inputs: analog
VDD (AVDD) and digital VDD (DVDD). Each AVDD input
should be decoupled with parallel 10F and 0.1F
ceramic-chip capacitors. These capacitors should be
as close to the pin as possible, and their opposite ends
should be as close to the ground plane as possible.
The DVDD pins should also have separate 10F and
0.1F capacitors adjacent to their respective pins. Try
to minimize analog load capacitance for proper opera-
tion. For best performance, it is recommended to
bypass CREF1 and CREF2 with low-ESR 0.1F capaci-
tors to AVDD.
The power-supply voltages should also be decoupled
with large tantalum or electrolytic capacitors at the
point they enter the PC board. Ferrite beads with addi-
tional decoupling capacitors forming a pi network can
also improve performance.
Chip Information
TRANSISTOR COUNT: 9464
SUBSTRATE CONNECTED TO AGND
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