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參數(shù)資料
| 型號(hào)： | MAX515ESA+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 4/16頁 |
| 文件大小： | 0K |
| 描述： | IC DAC 10BIT VOLT OUT 8-SOIC |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 設(shè)置時(shí)間： | 25µs |
| 位數(shù)： | 10 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SOIC |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 1 電壓，單極；1 電壓，雙極 |
| 采樣率（每秒）： | * |
MAX504/MAX515
Single-Supply Linearity
As with any amplifier, the MAX504/MAX515’s output
buffer offset can be positive or negative. When the off-
set is positive, it is easily accounted for (Figure 10).
However, when the offset is negative, the buffer output
cannot follow linearly when there is no negative supply.
In that case, the amplifier output (VOUT) remains at
ground until the DAC voltage is sufficient to overcome
the offset and the output becomes positive.
Normally, linearity is measured after accounting for
zero error and gain error. Since, in single-supply opera-
tion, the actual value of a negative offset is unknown, it
cannot be accounted for during test. Additionally, the
output buffer amplifier exhibits a nonlinearity near-zero
output when operating with a single supply. To account
for this nonlinearity in the MAX504/MAX515, linearity
and gain error are measured from code 3 to code
1023. The output buffer’s offset and nonlinearity do not
affect monotonicity, and these DACs are guaranteed
monotonic starting with code zero. In dual-supply oper-
ation, linearity and gain error are measured from code
0 to 1023.
Power-Supply Bypassing and
Ground Management
Best system performance is obtained with printed cir-
cuit boards that use separate analog and digital
ground planes. Wire-wrap boards are not recommend-
ed. The two ground planes should be connected
together at the low-impedance power-supply source.
DGND and AGND should be connected together at the
chip. For the MAX504 in single-supply applications,
connect VSS to AGND at the chip. The best ground
connection may be achieved by connecting the DAC's
DGND and AGND pins together and connecting that
point to the system analog ground plane. If the DAC's
DGND is connected to the system digital ground, digi-
tal noise may get through to the DAC’s analog portion.
Bypass VDD (and VSS in dual-supply mode) with a
0.1F ceramic capacitor connected between VDD and
AGND (and between VSS and AGND). Mount it with
short leads close to the device. Ferrite beads may also
be used to further isolate the analog and digital power
supplies.
Figures 11a and 11b illustrate the grounding and
bypassing scheme described.
Saving Power
When the DAC is not being used by the system, mini-
mize power consumption by setting the appropriate
code to minimize load current. For example, in bipolar
mode, with a resistive load to ground, set the DAC
code to mid-scale (see Table 3). If there is no output
load, minimize internal loading on the reference by set-
ting the DAC to all 0s (on the MAX504, use CLR).
Under this condition, REFIN is high impedance and the
op amp operates at its minimum quiescent current.
Due to these low currents, the output settling time for a
zero input code typically increases to 60s (100s
max).
5V, Low-Power, Voltage-Output,
Serial 10-Bit DACs
12
______________________________________________________________________________________
Figure 8. Bipolar Configuration (-2.048V to +2.048V Output)
Table 3. Bipolar (Offset Binary) Code
Table (-VREFIN to +VREFIN Output)
33F
REFIN
REFOUT
AGND
DGND
BIPOFF
RFB
VOUT
VOUT
-5V
+5V
MAX504
INPUT*
OUTPUT
1111
11(00)
1000
0000
01(00)
1000
0000
00(00)
0111
1111
11(00)
0000
01(00)
0000
00(00)
(+VREFIN)
511
512
(+VREFIN)
1
512
(-VREFIN)
1
512
(-VREFIN)
511
512
0V
(-VREFIN)
512
= -VREFIN
*
Write 10-bit data words with two sub-LSB 0s because the
DAC input latch is 12 bits wide.
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