參數(shù)資料
型號: MAX5150BCEE
廠商: Maxim Integrated Products
文件頁數(shù): 3/16頁
文件大?。?/td> 0K
描述: IC DAC DUAL V-OUT 13BIT 16-QSOP
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 100
設置時間: 16µs
位數(shù): 13
數(shù)據(jù)接口: 串行
轉換器數(shù)目: 2
電壓電源: 單電源
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 16-SSOP(0.154",3.90mm 寬)
供應商設備封裝: 16-QSOP
包裝: 管件
輸出數(shù)目和類型: 2 電壓,單極;2 電壓,雙極
采樣率(每秒): *
The address and control bits determine the MAX5150/
MAX5151's response, as outlined in Table 1.
The MAX5150/MAX5151's digital inputs are double
buffered, which allows any of the following: loading the
input register(s) without updating the DAC register(s),
updating the DAC register(s) from the input register(s),
or updating the input and DAC registers concurrently.
The address and control bits allow the DACs to act
independently.
The 16-bit data can be sent as two 8-bit packets (SPI,
Microwire), with CS low during this period. The address
and control bits determine which register will be updat-
ed, and the state of the registers when exiting shut-
down. The 3-bit address/control determines the
following:
registers to be updated
clock edge on which data is to be clocked out via
the serial-data output (DOUT)
state of the user-programmable logic output
configuration of the device after shutdown.
The general timing diagram of Figure 5 illustrates how
data is acquired. Driving CS low enables the device to
receive data. Otherwise, the interface control circuitry is
disabled. With CS low, data at DIN is clocked into the
register on the rising edge of SCLK. As CS goes high,
data is latched into the input and/or DAC registers
depending on the address and control bits. The maxi-
mum clock frequency guaranteed for proper operation
is 10MHz. Figure 6 depicts a more detailed timing dia-
gram of the serial interface.
MAX5150/MAX5151
Low-Power, Dual, 13-Bit Voltage-Output DACs
with Serial Interface
DIN
SCLK
CS
MOSI
SCK
I/O
SPI/QSPI
PORT
SS
+5V
CPOL = 0, CPHA = 0
MAX5150
MAX5151
Figure 3. Connections for SPI/QSPI
Figure 5. Serial-Interface Timing Diagram
CS
SCLK
DIN
COMMAND
EXECUTED
9
8
16
1
C1
A0
D0
C0
D12 D11 D10
D9
D6
D5
D4
D3
D2
D1
D8
D7
______________________________________________________________________________________
11
MSB.......Data Bits.........LSB
D12.................................D0
13 Data Bits
16 Bits of Serial Data
Control Bits
C1, C0
Address Bits
MSB ..................................................................................LSB
A0
1 Address/2 Control Bits
Figure 4. Serial-Data Format
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