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參數(shù)資料
| 型號： | MAX5139GTE+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 2/17頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC V-OUT 12BIT 1CH 16-TQFN |
| 產(chǎn)品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 2,500 |
| 設置時間： | 5µs |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | DSP，I²C，MICROWIRE?，并行，QSPI?，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-WFQFN 裸露焊盤 |
| 供應商設備封裝： | 16-TQFN（3x3） |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 1 電壓，單極；1 電壓，雙極 |
| 采樣率（每秒）： | * |
AVDD as Reference
Connect AVDD to REFI to use AVDD as the reference
voltage. Leave REFO unconnected.
Serial Interface
The MAX5138/MAX5139 3-wire serial interface is com-
patible with MICROWIRE, SPI, QSPI, and DSPs (Figures
2, 3). The interface provides three inputs, SCLK, CS,
and DIN and one output, READY. Use READY to verify
communication or to daisy-chain multiple devices (see
the READY section). READY is capable of driving a
20pF load with a 30ns (max) delay from the falling edge
of SCLK. The chip-select input (CS) frames the serial
data loading at DIN. Following a chip-select input’s
high-to-low transition, the data is shifted synchronously
and latched into the input register on each falling edge
of the serial-clock input (SCLK). Each serial word is 24
bits. The first 8 bits are the control word followed by 16
data bits (MSB first), as shown in Table 1. The serial
input register transfers its contents to the input registers
after loading 24 bits of data. To initiate a new data
transfer, drive CS high and keep CS high for a minimum
of 33ns before the next write sequence. The SCLK can
be either high or low between CS write pulses. Figure 1
shows the timing diagram for the complete 3-wire serial-
interface transmission.
The MAX5138/MAX5139 digital input is double buffered.
Depending on the command issued through the serial
interface, the input register can be loaded without affect-
ing the DAC register using the write command. To update
the DAC register, either pulse the LDAC input low, or use
the software LDAC command. Use the writethrough com-
mands (see Table 1) to update the DAC output immedi-
ately after the data is received. Only use the writethrough
command to update the DAC output immediately.
Low-Power, Single, 16-/12-Bit,
Buffered Voltage-Output DACs
10
Maxim Integrated
MAX5138/MAX5139
24-BIT WORD
CONTROL BITS
DATA BITS
MSB
LSB
C7 C6 C5 C4 C3 C2 C1 C0 D15 D14 D13 D12 D11 D10 D9
D8
D7
D6–D0
DESC
FUNCTION
0
X
NOP
No operation.
0
1
X
DAC
X
LDAC
Set DAC = 1 to move
contents of input to DAC
register. Setting DAC = 0
results in no operation.
0
1
0
X
CLR
Software clear.
0
1
X
DAC READY_EN
X
Power
Control
Set DAC = 1 to power
down DAC. Set
READY_EN = 1 to
enable
READY. Setting
DAC = 0 results in no
operation.
0
1
0
1
0
LIN
0
Linearity Optimize DAC linearity.
0
1
X
X DAC D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
Write
Write to selected input
registers (DAC output
not affected). Setting
DAC = 0 results in no
operation.
0
1
X
X DAC D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
Write-
through
Write to selected input
and DAC register,
DAC output updated
(writethrough). Setting
DAC = 0 results in no
operation.
0
1
0
X
NOP
No operation.
Table 1. Operating Mode Truth Table
*
For the MAX5139, D3–D0 are X = don’t-care bits.
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相關(guān)代理商/技術(shù)參數(shù) |
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