參數(shù)資料
型號: MAX3420EETG+T
廠商: Maxim Integrated Products
文件頁數(shù): 9/22頁
文件大小: 0K
描述: IC USB PERIPH CONTROLLER 24TQFN
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 2,500
控制器類型: USB 外設控制器
接口: USB/串行
電源電壓: 3 V ~ 3.6 V
電流 - 電源: 15mA
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-WFQFN 裸露焊盤
供應商設備封裝: 24-TQFN-EP(4x4)
包裝: 帶卷 (TR)
配用: MAX3420EEVKIT-2+-ND - EVAL KIT FOR MAX3420E
(5) To write SPI data, the SPI master keeps its output
driver on and clocks subsequent bytes into the
MOSI pin. To read SPI data, after the eighth clock
cycle the SPI master tri-states its output driver and
begins clocking in data bytes from the MOSI pin.
(6) The SPI master terminates the SPI cycle by return-
ing SS high.
Figures 8 and 9 show timing diagrams for full- and half-
duplex operation.
USB Serial-Interface Engine
The serial-interface engine (SIE) does most of the
detailed work required by USB protocol:
USB packet PID detection and checking
CRC check and generation
Automatic retries in case of errors
USB packet generation
NRZI data encoding and decoding
Bit stuffing and unstuffing
Various USB error condition detection
USB bus reset, suspend, and wake-up detection
USB resume signaling
Automatic flow control (NAK)
PLL
An internal PLL multiplies the 12MHz oscillator signal
by four to produce an internal 48MHz clock. When the
chip is powered down, the oscillator is turned off to
conserve power. When repowered, the oscillator and
PLL require time to stabilize and lock. The OSCOKIRQ
interrupt bit is used to indicate to the SPI master that
the clocking system is stable and ready for operation.
Power Management
According to USB rev. 2.0 specification, when a USB
host stops sending traffic for at least 3 milliseconds to a
peripheral, the peripheral must enter a power-down
state called SUSPEND. Once suspended, the peripher-
al must have enough of its internal logic active to rec-
ognize when the host resumes signaling, or if enabled
for remote wakeup, that the SPI master wishes to signal
a resume event. The following sections titled
Suspend
and
Wakeup and USB Resume describe how the SPI
master coordinates with the MAX3420E to accomplish
this power management.
Suspend
After three milliseconds of USB bus inactivity, a USB
peripheral is required to enter the USB suspend state
and draw no more than 500A of supply current. To
accomplish this, after three milliseconds of USB bus
inactivity, the MAX3420E sets the SUSPIRQ bit in the
USBIRQ (R13) register and asserts the INT output, if
SUSPIE = 1 and IE = 1. The SPI master must do any
necessary power-saving housekeeping and then set
the PWRDOWN bit in the USBCTL (R15) register. This
instructs the MAX3420E to enter a power-down state, in
which it does the following:
Stops the 12MHz oscillator
Keeps the INT output active (according to the
mode set in the PINCTL (R17) register)
Monitors the USB D+ line for bus activity
Monitors the SPI port for any traffic
Note that the MAX3420E does not automatically enter
a power-down state after three milliseconds of bus
inactivity. This allows the SPI master to perform any
USB Peripheral Controller
with SPI Interface
SS
MISO
MOSI
SCLK
SPI MODE 0,0 (CPOL = 0, CPHA = 0)
SUSPIRQ
URESIRQ
SUDAVIRQ
IN3BAVIRQ
IN2BAVIRQ
REG4
REG3
REG2
REG1
REG0
0
DIR
ACKSTAT
OUT1DAVIRQ OUT0DAVIRQ
IN0BAVIRQ
X
Figure 15. SPI Port in Full-Duplex Mode
MAX3420E
Maxim Integrated
17
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