- 鎮ㄧ従(xi脿n)鍦ㄧ殑浣嶇疆锛�璨疯常IC缍�(w菐ng) > PDF鐩寗11587 > MAX3420EETG+ (Maxim Integrated Products)IC USB PERIPH CONTROLLER 24TQFN PDF璩囨枡涓嬭級
鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | MAX3420EETG+ |
| 寤犲晢锛� | Maxim Integrated Products |
| 鏂囦欢闋佹暩(sh霉)锛� | 4/22闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC USB PERIPH CONTROLLER 24TQFN |
| 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 75 |
| 鎺у埗鍣ㄩ鍨嬶細 | USB 澶栬ō(sh猫)鎺у埗鍣� |
| 鎺ュ彛锛� | USB/涓茶 |
| 闆绘簮闆诲锛� | 3 V ~ 3.6 V |
| 闆绘祦 - 闆绘簮锛� | 15mA |
| 宸ヤ綔婧害锛� | -40°C ~ 85°C |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 24-WFQFN 瑁搁湶鐒婄洡 |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 24-TQFN-EP锛�4x4锛� |
| 鍖呰锛� | 绠′欢 |
| 鐢�(ch菐n)鍝佺洰閷勯爜闈細 | 1407 (CN2011-ZH PDF) |
| 閰嶇敤锛� | MAX3420EEVKIT-2+-ND - EVAL KIT FOR MAX3420E |
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USB Peripheral Controller
with SPI Interface
Typical Operating Characteristics
(VCC = +3.3V, VL = +3.3V, TA = +25掳C.)
Detailed Description
The MAX3420E contains the digital logic and analog
circuitry necessary to implement a full-speed USB
peripheral that complies with the USB specification rev
2.0. ESD protection of 卤15kV is provided on D+, D-,
and VBCOMP. The MAX3420E features an internal USB
transceiver and an internal 1.5k
惟 resistor that connects
between D+ and VCC under the control of a register bit
(CONNECT). This allows a USB peripheral to control
the logical connection to the USB host. Any SPI master
can communicate with the MAX3420E through the SPI
slave interface that operates in SPI mode (0,0) or (1,1).
An SPI master accesses the MAX3420E by reading and
writing to internal registers. A typical data transfer con-
sists of writing a first byte that sets a register address
and direction with additional bytes reading or writing
data to the register or internal FIFO.
The MAX3420E contains 384 bytes of endpoint buffer
memory, implementing the following endpoints:
EP0: 64-byte bidirectional CONTROL endpoint
EP1: 2 x 64-byte double-buffered BULK/INT
OUT endpoint
EP2: 2 x 64-byte double-buffered BULK/INT IN
endpoint
EP3: 64-byte BULK/INT IN endpoint
The choice to use EP1, EP2, EP3 as BULK or INTER-
RUPT endpoints is strictly a function of the endpoint
descriptors that the SPI master returns to the USB host
during enumeration.
The MAX3420E register set and SPI interface is optimized
to reduce SPI traffic. An interrupt output pin, INT, notifies
the SPI master when USB service is required: when a
packet arrives, a packet is sent, or the host suspends or
resumes bus activity. Double-buffered endpoints help
sustain bandwidth by allowing data to move concurrently
over USB and the SPI interface.
VCC
Power the USB transceiver by applying a positive 3.3V
supply to VCC. Bypass VCC to GND with a 1.0F
ceramic capacitor as close to the VCC pin as possible.
VL
The MAX3420E digital core is powered though the VL
pin. VL also acts as a reference level for the SPI inter-
face and all other inputs and outputs. Connect VL to the
system鈥檚 logic-level power supply. Internal level transla-
tors and VL allow the SPI interface and all general-pur-
pose inputs and outputs to operate at a system voltage
between 1.71V and 3.6V.
VBCOMP
The MAX3420E features a USB VBUS detector input,
VBCOMP. The VBCOMP pin can withstand input volt-
ages up to 6V. Bypass VBCOMP to GND with a 1.0F
ceramic capacitor. According to USB specification rev
2.0, a self-powered USB device must not power the
1.5k
惟 pullup resistor on D+ if the USB host turns off
VBUS. VBCOMP is internally connected to a voltage
comparator so that the SPI master can detect the loss
of VBUS (through an interrupt (INT) or checking a bit
EYE DIAGRAM
MAX3420E
toc01
4
1
0
-1
0
1020304050607080
2
3
TIME (ns)
D+
AND
D-
(V)
MAX3420E
12
Maxim Integrated
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鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| MAX3420EETG+ | 鍔熻兘鎻忚堪:澶栧湇椹�(q奴)鍕曞櫒鑸囧師浠� - PCI USB Peripheral Controller w/SPI RoHS:鍚� 鍒堕€犲晢:PLX Technology 宸ヤ綔闆绘簮闆诲: 鏈€澶у伐浣滄韩搴�: 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FCBGA-1156 灏佽:Tray |
| MAX3420EETG+T | 鍔熻兘鎻忚堪:澶栧湇椹�(q奴)鍕曞櫒鑸囧師浠� - PCI USB Peripheral Controller w/SPI RoHS:鍚� 鍒堕€犲晢:PLX Technology 宸ヤ綔闆绘簮闆诲: 鏈€澶у伐浣滄韩搴�: 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FCBGA-1156 灏佽:Tray |
| MAX3420EETG-T | 鍔熻兘鎻忚堪:澶栧湇椹�(q奴)鍕曞櫒鑸囧師浠� - PCI RoHS:鍚� 鍒堕€犲晢:PLX Technology 宸ヤ綔闆绘簮闆诲: 鏈€澶у伐浣滄韩搴�: 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FCBGA-1156 灏佽:Tray |
| MAX3420EEVKIT | 鍒堕€犲晢:Maxim Integrated Products 鍔熻兘鎻忚堪:MAX3420E EVAL KIT - Bulk |
| MAX3420EEVKIT-2+ | 鍔熻兘鎻忚堪:鐣岄潰闁嬬櫦(f膩)宸ュ叿 MAX3420E Eval Kit RoHS:鍚� 鍒堕€犲晢:Bourns 鐢�(ch菐n)鍝�:Evaluation Boards 椤炲瀷:RS-485 宸ュ叿鐢ㄤ簬瑭曚及:ADM3485E 鎺ュ彛椤炲瀷:RS-485 宸ヤ綔闆绘簮闆诲:3.3 V |
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