- 鎮ㄧ従(xi脿n)鍦ㄧ殑浣嶇疆锛�璨疯常IC缍�(w菐ng) > PDF鐩寗11587 > MAX3420EETG+ (Maxim Integrated Products)IC USB PERIPH CONTROLLER 24TQFN PDF璩囨枡涓嬭級
鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | MAX3420EETG+ |
| 寤犲晢锛� | Maxim Integrated Products |
| 鏂囦欢闋佹暩(sh霉)锛� | 3/22闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC USB PERIPH CONTROLLER 24TQFN |
| 鐢�(ch菐n)鍝佸煿瑷撴ā濉婏細 | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 妯欐簴鍖呰锛� | 75 |
| 鎺у埗鍣ㄩ鍨嬶細 | USB 澶栬ō鎺у埗鍣� |
| 鎺ュ彛锛� | USB/涓茶 |
| 闆绘簮闆诲锛� | 3 V ~ 3.6 V |
| 闆绘祦 - 闆绘簮锛� | 15mA |
| 宸ヤ綔婧害锛� | -40°C ~ 85°C |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 24-WFQFN 瑁搁湶鐒婄洡 |
| 渚涙噳鍟嗚ō鍌欏皝瑁濓細 | 24-TQFN-EP锛�4x4锛� |
| 鍖呰锛� | 绠′欢 |
| 鐢�(ch菐n)鍝佺洰閷勯爜闈細 | 1407 (CN2011-ZH PDF) |
| 閰嶇敤锛� | MAX3420EEVKIT-2+-ND - EVAL KIT FOR MAX3420E |
绗�1闋�绗�2闋�鐣跺墠绗�3闋�绗�4闋�绗�5闋�绗�6闋�绗�7闋�绗�8闋�绗�9闋�绗�10闋�绗�11闋�绗�12闋�绗�13闋�绗�14闋�绗�15闋�绗�16闋�绗�17闋�绗�18闋�绗�19闋�绗�20闋�绗�21闋�绗�22闋�
USB Peripheral Controller
with SPI Interface
Test Circuits and Timing Diagrams
Figure 6. Rise and Fall Times
VOL
VOH
tRISE
tFALL
90%
10%
Figure 7. Load for D+/D- AC Measurements
MAX3420E
D+ OR D-
TEST
POINT
33
惟
15k
惟
CL
SCLK
SS
MOSI
MISO
tDS
tDH
tCL
tDO
tCH
tT
HIGH
IMPEDANCE
8
1
2
9
10
16
tL
tCSS
tCSW
tCP
HIGH
IMPEDANCE
Figure 9. SPI Bus Timing Diagram (Half-Duplex Mode, SPI Mode (0,0))
SCLK
MOSI
MISO
NOTES:
1) DURING THE FIRST 8 CLOCKS CYCLES, THE MOSI PIN IS HIGH IMPEDANCE AND THE SPI MASTER DRIVES DATA ONTO THE MOSI PIN. SETUP AND HOLD TIMES ARE THE SAME AS
FOR FULL-DUPLEX MODE.
2) FOR SPI WRITE CYCLES, THE MOSI PIN CONTINUES TO BE HIGH IMPEDANCE AND THE EXTERNAL MASTER CONTINUES TO DRIVE MOSI.
3) FOR SPI READ CYCLES, AFTER THE 8TH CLOCK-RISING EDGE, THE MAX3420E STARTS DRIVING THE MOSI PIN AFTER TIME tON. THE EXTERNAL MASTER MUST TURN
OFF ITS DRIVER TO THE MOSI PIN BEFORE tON TO AVOID CONTENTION. PROPAGATION DELAYS ARE THE SAME AS FOR THE MOSI PIN IN FULL-DUPLEX MODE.
tDS
tDH
tCL
tCH
tDI
tOFF
tT
SS
HI-Z
8
1
2
9
10
16
tL
tCSW
tON
tCP
HIGH IMPEDANCE
Figure 8. SPI Bus Timing Diagram (Full-Duplex Mode, SPI Mode (0,0))
MAX3420E
11
Maxim Integrated
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鐩搁棞浠ｇ悊鍟�/鎶€琛撳弮鏁�(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| MAX3420EETG+ | 鍔熻兘鎻忚堪:澶栧湇椹�(q奴)鍕曞櫒鑸囧師浠� - PCI USB Peripheral Controller w/SPI RoHS:鍚� 鍒堕€犲晢:PLX Technology 宸ヤ綔闆绘簮闆诲: 鏈€澶у伐浣滄韩搴�: 瀹夎棰ㄦ牸:SMD/SMT 灏佽 / 绠遍珨:FCBGA-1156 灏佽:Tray |
| MAX3420EETG+T | 鍔熻兘鎻忚堪:澶栧湇椹�(q奴)鍕曞櫒鑸囧師浠� - PCI USB Peripheral Controller w/SPI RoHS:鍚� 鍒堕€犲晢:PLX Technology 宸ヤ綔闆绘簮闆诲: 鏈€澶у伐浣滄韩搴�: 瀹夎棰ㄦ牸:SMD/SMT 灏佽 / 绠遍珨:FCBGA-1156 灏佽:Tray |
| MAX3420EETG-T | 鍔熻兘鎻忚堪:澶栧湇椹�(q奴)鍕曞櫒鑸囧師浠� - PCI RoHS:鍚� 鍒堕€犲晢:PLX Technology 宸ヤ綔闆绘簮闆诲: 鏈€澶у伐浣滄韩搴�: 瀹夎棰ㄦ牸:SMD/SMT 灏佽 / 绠遍珨:FCBGA-1156 灏佽:Tray |
| MAX3420EEVKIT | 鍒堕€犲晢:Maxim Integrated Products 鍔熻兘鎻忚堪:MAX3420E EVAL KIT - Bulk |
| MAX3420EEVKIT-2+ | 鍔熻兘鎻忚堪:鐣岄潰闁嬬櫦(f膩)宸ュ叿 MAX3420E Eval Kit RoHS:鍚� 鍒堕€犲晢:Bourns 鐢�(ch菐n)鍝�:Evaluation Boards 椤炲瀷:RS-485 宸ュ叿鐢ㄤ簬瑭曚及:ADM3485E 鎺ュ彛椤炲瀷:RS-485 宸ヤ綔闆绘簮闆诲:3.3 V |
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