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參數(shù)資料
| 型號(hào)： | MAX31826MUA+T |
| 廠商： | Maxim Integrated |
| 文件頁(yè)數(shù)： | 10/22頁(yè) |
| 文件大?。?/td> | 1648K |
| 描述： | IC TEMP SENSOR DIGITAL 8UMAX |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 系列： | 1-Wire® |
| 功能： | 溫度監(jiān)控系統(tǒng)（傳感器） |
| 傳感器類(lèi)型： | 內(nèi)部 |
| 感應(yīng)溫度： | -55°C ~ 125°C |
| 精確度： | ±2°C |
| 拓?fù)洌?/td> | 寄存器庫(kù)，變簽式暫存器 |
| 輸出類(lèi)型： | 1-Wire? |
| 輸出警報(bào)： | 無(wú) |
| 輸出風(fēng)扇： | 無(wú) |
| 電源電壓： | 3 V ~ 3.7 V |
| 工作溫度： | -55°C ~ 125°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 8-TSSOP，8-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-uMAX |
| 包裝： | 帶卷 (TR) |
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Maxim Integrated Products 10
MAX31826
1-Wire Digital Temperature Sensor
with 1Kb Lockable EEPROM
CRC Generation
CRC bytes are provided as part of the devices 64-bit
ROM code, in the 9th byte of Scratchpad 1, and for
Scratchpad 2 values. The ROM code CRC is calculated
from the first 56 bits of the ROM code and is contained in
the most significant byte of the ROM. The two scratchpad
CRCs are calculated from the data in each scratchpad,
and therefore changes when the data in it associated
scratchpad changes. The CRCs provide the bus mas-
ter with a method of data validation when data is read
from the device. To verify that data has been read cor-
rectly, the bus master must recalculate the CRC from
the received data and then compare this value to either
the ROM code CRC (for ROM reads) or to the scratch-
pads CRC (for scratchpad reads). If the calculated CRC
matches the read CRC, the data has been received
error-free. The comparison of CRC values and the deci-
sion to continue with an operation are determined entirely
by the bus master. There is no circuitry inside the device
that prevents a command sequence from proceeding if
the device CRC (ROM or scratchpad) does not match the
value generated by the bus master.
The equivalent polynomial function of the CRC (ROM or
scratchpad) is:
CRC = X
8
+ X
5
+ X
4
+ 1
The bus master can recalculate the CRC and compare it
to the CRC values from the device using the polynomial
generator shown in Figure 5. This circuit consists of a
shift register and XOR gates, and the shift register bits
are initialized to 0. Starting with the least significant bit
of the ROM code or the least significant bit of byte 0 in
the scratchpad, one bit at a time should shifted into the
shift register. After shifting in the 56th bit from the ROM
or the most significant bit of byte 7 from the Scratchpad 1
or byte 10 from Scratchpad 2, the polynomial generator
contains the recalculated CRC. Next, the 8-bit ROM code
or scratchpad CRC from the device must be shifted into
the circuit. At this point, if the recalculated CRC was
correct, the shift register contains all zeros. Additional
information about the Maxim 1-Wire CRC is available in
Application Note 27: Understanding and Using Cyclic
Redundancy Checks with Maxim iButton
?/DIV>
Products.
1-Wire Bus System
The 1-Wire bus system uses a single bus master to con-
trol one or more slave devices. The MAX31826 is always
a slave. When there is only one slave on the bus, the
system is referred to as a single-drop system; the system
is multidrop if there are multiple slaves on the bus. All
data and commands are transmitted least significant bit
first over the 1-Wire bus.
The following discussion of the 1-Wire bus system is
broken down into three topics: hardware configuration,
transaction sequence, and 1-Wire signaling (signal types
and timing).
Hardware Configuration
The 1-Wire bus has by definition only a single data line.
Each device (master or slave) interfaces to the data line
by using an open-drain or three-state port. This allows
each device to release the data line when the device
is not transmitting data so the bus is available for use by
another device. The devices 1-Wire port (DQ) is open
drain with an internal circuit equivalent to that shown in
Figure 6.
Figure 5. CRC Generator
iButton is a registered trademark of Maxim Integrated Products, Inc.
1ST
STAGE
2ND
STAGE
3RD
STAGE
4TH
STAGE
7TH
STAGE
8TH
STAGE
6TH
STAGE
5TH
STAGE
X
0
X
1
X
2
X
3
X
4
POLYNOMIAL = X
8
+ X
5
+ X
4
+ 1
INPUT DATA
X
5
X
6
X
7
X
8
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