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參數資料
| 型號： | MAX3111ECNI+G36 |
| 廠商： | Maxim Integrated Products |
| 文件頁數： | 7/31頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC UART SPI COMPAT 28-DIP |
| 產品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 14 |
| 特點： | 收發(fā)器 |
| 通道數： | 1，UART |
| 規(guī)程： | RS232，RS485 |
| 電源電壓： | 3 V ~ 3.6 V |
| 帶IrDA 編碼器/解碼器： | 是 |
| 帶故障啟動位檢測功能： | 是 |
| 帶CMOS： | 是 |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 28-DIP（0.300"，7.62mm） |
| 供應商設備封裝： | 28-PDIP |
| 包裝： | 管件 |
| 產品目錄頁面： | 1404 (CN2011-ZH PDF) |
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Write Configuration Register (D15, D14 = 1, 1)
Configure the UART by writing a 16-bit word to the write
configuration register, which programs the baud rate,
data word length, parity enable, and enable of the 8-
word receive FIFO. In this mode, bits 15 and 14 of the
DIN configuration word are both required to be 1 in
order to enable the write configuration mode. Bits 13–0
of the DIN configuration word set the configuration of
the UART. Table 2 shows the bit assignment for the
write configuration register. The write configuration reg-
ister allows selection between normal UART timing and
IrDA timing, provides shutdown control, and contains
four interrupt mask bits.
Using the write configuration register clears the receive
FIFO and the R, T, RA/FE, D0r–D7r, D0t–D7t, Pr, and Pt
registers. RTS and CTS remain unchanged. The new
configuration is valid on CS’s rising edge if the transmit
buffer is empty (T = 1) and transmission is over. If the
latest transmission has not been completed (T = 0), the
registers are updated when the transmission is over.
The write configuration register bits (FEN, SHDNi, IR,
ST, PE, L, B3–B0) take effect after the current transmis-
sion is over. The mask bits (TM, RM, PM, RAM) take
effect immediately after SCLK’s 16th rising edge.
Bits 15 and 14 of the DOUT write configuration (R and
T) are sent out of the MAX3110E/MAX3111E along with
14 trailing zeros. The use of the R and T bits is optional,
but ignore the 14 trailing zeros.
Warning! The UART requires stable crystal oscillator
operation before configuration (typically ~25ms after
power-up). Upon power-up, compare the write configu-
ration bits with the read configuration bits in a software
loop until both match. This ensures that the oscillator is
stable and that the UART is configured correctly.
Read Configuration Register (D15, D14 = 0, 1)
The read configuration register is used to read back the
last configuration written to the UART. In this register,
bits 15 and 14 of the DIN configuration word are
required to be 0 and 1, respectively, to enable the read
configuration mode. Bits 13–1 of the DIN word should
be zeros, and bit 0 is the test bit to put the UART in test
mode (see the
Test Mode section). Table 3 shows the
bit assignment for the read configuration register.
Test Mode
The device enters a test mode if bit 0 of the DIN config-
uration word equals one when doing a read configura-
tion. In this mode, if CS = 0, the RTS pin transmits a
clock that is 16-times the baud rate. The TX pin is low
as long as CS remains low while in test mode. Table 3
shows the bit assignment for the read configuration
register.
Write Data Register (D15, D14 = 1, 0)
Use the write data register for transmitting to the TX-
buffer and receiving from the RX buffer (and RX FIFO
when enabled). When using this register, the DIN and
DOUT write data words are used simultaneously, and
bits 13–11 for both the DIN and DOUT write data words
are meaningless zeros. The DIN write data word con-
tains the data that is being transmitted, and the DOUT
write data word contains the data that is being received
from the RX FIFO. Table 4 shows the bit assignment for
the write data mode. To change the RTS pin’s output
state without transmitting data, set the TE bit high. If
performing a write data operation, the R bit will clear on
the falling edge of SCLK’s 16th clock pulse if no new
data is available.
Read Data Register (D15, D14 = 0, 0)
Use the read data register for receiving data from the
RX FIFO. When using this register, bits 15 and 14 of
DIN are both required to be 0. Bits 13–0 of the DIN
read-data word should be zeros. Table 5 shows the bit
assignments for the read data mode. Reading data
clears the R bit and interrupt IRQ. If performing a read
data operation, the R bit will clear on the falling edge of
SCLKs 16th clock pulse if no new data is available.
SPI/MICROWIRE-Compatible UART and ±15kV ESD-
Protected RS-232 Transceivers with Internal Capacitors
Maxim Integrated
15
MAX3110E/MAX3111E
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