參數(shù)資料
型號(hào): MAX3100ETG+
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: 微控制器/微處理器
英文描述: 1 CHANNEL(S), 230.4K bps, SERIAL COMM CONTROLLER, QCC24
封裝: ROHS COMPLIANT, TQFN-24
文件頁數(shù): 20/24頁
文件大?。?/td> 286K
代理商: MAX3100ETG+
MAX3100
SPI/Microwire-Compatible
UART in QSOP-16
_______________________________________________________________________________________
5
Detailed Description
The MAX3100 universal asynchronous receiver transmitter
(UART) interfaces the SPI/Microwire-compatible, synchro-
nous serial data from a microprocessor (P) to asynchro-
nous, serial-data communication ports (RS-232, RS-485,
IrDA). Figure 2 shows the MAX3100 functional diagram.
The MAX3100 combines a simple UART and a baud-rate
generator with an SPI interface and an interrupt genera-
tor. Configure the UART by writing a 16-bit word to a
write-configuration register, which contains the baud rate,
data-word length, parity enable, and enable of the 8-word
receive first-in/first-out (FIFO). The write configuration
selects between normal UART timing and IrDA timing,
controls shutdown, and contains 4 interrupt mask bits.
Transmit data by writing a 16-bit word to a write-data
register, where the last 7 or 8 bits are actual data to be
transmitted. Also included is the state of the transmitted
parity bit (if enabled). This register controls the state of
the
RTS output pin. Received words generate an inter-
rupt if the receive-bit interrupt is enabled.
Read data from a 16-bit register that holds the oldest
data from the receive FIFO, the received parity data,
and the logic level at the
CTS input pin. This register
also contains a bit that is the framing error in normal
operation and a receive-activity indicator in shutdown.
The baud-rate generator determines the rate at which the
transmitter and receiver operate. Bits B0 to B3 in the
write-configuration register determine the baud-rate divi-
sor (BRD), which divides down the X1 oscillator frequen-
cy. The baud clock is 16 times the data rate (baud rate).
The transmitter section accepts SPI/Microwire data, for-
mats it, and transmits it in asynchronous serial format
from the TX output. Data is loaded into the transmit-
buffer register from the SPI/Microwire interface. The
MAX3100 adds start and stop bits to the data and
clocks the data out at the selected baud rate (Table 7).
Pin Description
PIN
QSOP
DIP
TQFN-EP
NAME
FUNCTION
1
23
DIN
SPI/Microwire Serial-Data Input. Schmitt-trigger input.
2
DOUT
SPI/Microwire Serial-Data Output. High impedance when
CS is high.
3
SCLK
SPI/Microwire Serial-Clock Input. Schmitt-trigger input.
444
CS
Active-Low Chip-Select Input. DOUT goes high impedance when
CS is high,
IRQ, TX, and RTS are always active. Schmitt-trigger input.
655
IRQ
Active-Low Interrupt Output. Open-drain interrupt output to microprocessor.
768
SHDN
Hardware-Shutdown Input. When shut down (
SHDN = 0), the oscillator turns
off immediately without waiting for the current transmission to end, reducing
supply current to just leakage currents.
8
7
9
GND
Ground
98
10
X2
Crystal Connection. Leave X2 unconnected for external clock. See Crystal-
Oscillator Operation—X1, X2 Connection section.
10
9
11
X1
Crystal Connection. X1 also serves as an external clock input. See Crystal-
Oscillator Operation—X1, X2 Connection section.
11
10
15
CTS
General-Purpose Active-Low Input. Read via the
CTS register bit; often used
for RS-232 clear-to-send input (Table 1).
13
11
16
RTS
General-Purpose Active-Low Output. Controlled by the
CTS register bit. Often
used for RS-232 request-to-send output or RS-485 driver enable.
14
12
17
RX
Asynchronous Serial-Data (receiver) Input. The serial information received
from the modem or RS-232/RS-485 receiver. A transition on RX while in
shutdown generates an interrupt (Table 5).
15
13
21
TX
Asynchronous Serial-Data (transmitter) Output
16
14
22
VCC
Positive Supply Pin (2.7V to 5.5V)
5, 12
1, 6, 7, 12,
13, 14, 18,
19, 20, 24
N.C.
No Connection. Not internally connected.
EP
Exposed Pad. Connect EP to ground or leave unconnected.
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