參數資料
型號: MAX3023EUD+T
廠商: Maxim Integrated Products
文件頁數: 3/18頁
文件大小: 0K
描述: IC TRANSLATOR LVL 100MBPS 14TSSO
產品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 2,500
邏輯功能: 變換器,雙向,3 態(tài)
位數: 4
輸入類型: 邏輯
輸出類型: 邏輯
數據速率: 100Mbps
通道數: 4
輸出/通道數目: 1
差分 - 輸入:輸出: 無/無
傳輸延遲(最大): 6ns
電源電壓: 1.65 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
封裝/外殼: 14-TSSOP(0.173",4.40mm 寬)
供應商設備封裝: 14-TSSOP
包裝: 帶卷 (TR)
MAX13013/MAX13014/MAX3023
+1.2V to +3.6V, 0.1A, 100Mbps,
Single-/Dual-/Quad-Level Translators
______________________________________________________________________________________
11
Figure 6 shows a graph of typical input current versus
input voltage.
Output Load Requirements
The MAX13013/MAX13014/MAX3023 I/O are designed to
drive CMOS inputs. Do not load the I/O lines with a resis-
tive load less than 25k
Ω. Also, do not place an RC circuit
at the input of these devices to slow down the edges. If a
slower rise/fall time is required, refer to the
MAX3000E/MAX3001E logic-level-translators data sheet.
For I2C level translation, refer to the MAX3372E-
MAX3379E/MAX3390E–MAX3393E data sheet.
Enable Inputs
The MAX13013 single-, the MAX13014 dual- and the
MAX3023 (UCSP package) quad-level translators feature
an EN input. The MAX3023 (TSSOP package) quad-level
translator features both EN and EN inputs (see Table 2
for operating mode). Note that the MAX3023 (TSSOP
package) has internal pullup and pulldown circuitry on
EN and EN, respectively. If left unconnected, EN is pulled
up to VL and EN is pulled down to GND.
Applications Information
Power-Supply Decoupling
To reduce ripple and the chance of introducing data
errors, bypass VL and VCC to ground with a 0.1F
ceramic capacitor. Place all capacitors as close to the
power-supply inputs as possible.
Unidirectional vs. Bidirectional Level
Translator
The MAX13013/MAX13014/MAX3023 bidirectional
translators can operate as a unidirectional device to
translate signals without inversion. These devices pro-
vide the smallest solution (UCSP package) for unidirec-
tional level translation without inversion.
UCSP Applications Information
For the latest application details on UCSP construction,
dimensions, tape carrier information, PC board tech-
niques, bump-pad layout, and recommended reflow tem-
perature profiles, as well as the latest information on
reliability testing results, go to Maxim’s web site at
www.maxim-ic.com/ucsp to find the Application Note:
UCSP—A Wafer-Level Chip-Scale Package.
Table 2. MAX3023 (TSSOP Package)
Operating Mode
EN
EN
OPERATING MODE
0
Both I/O VL_ and I/O VCC_ are in tri-state.
VL
0
Normal operation.
0VL
Both I/O VL_ and I/O VCC_ are in tri-state.
VL
Both I/O VL_ and I/O VCC_ are in tri-state.
VIN
VTH_IN / RIN*
-(VS - VTH_IN) /
RIN*
IIN
VS
WHERE VS = VCC OR VL
*RIN = 4k
Ω WHEN DRIVING VL SIDE; RIN = 150Ω WHEN DRIVING VCC SIDE.
0
VTH_IN
Figure 6. Typical IIN vs. VIN
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