參數(shù)資料
型號: MAX3023EUD+T
廠商: Maxim Integrated Products
文件頁數(shù): 2/18頁
文件大小: 0K
描述: IC TRANSLATOR LVL 100MBPS 14TSSO
產品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 2,500
邏輯功能: 變換器,雙向,3 態(tài)
位數(shù): 4
輸入類型: 邏輯
輸出類型: 邏輯
數(shù)據速率: 100Mbps
通道數(shù): 4
輸出/通道數(shù)目: 1
差分 - 輸入:輸出: 無/無
傳輸延遲(最大): 6ns
電源電壓: 1.65 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
封裝/外殼: 14-TSSOP(0.173",4.40mm 寬)
供應商設備封裝: 14-TSSOP
包裝: 帶卷 (TR)
MAX13013/MAX13014/MAX3023
+1.2V to +3.6V, 0.1A, 100Mbps,
Single-/Dual-/Quad-Level Translators
10
______________________________________________________________________________________
Detailed Description
The MAX13013/MAX13014/MAX3023 logic-level trans-
lators provide the level shifting necessary to allow
100Mbps data transfer in a multivoltage system.
Externally applied voltages, VCC and VL, set the logic
levels on either side of the device. Logic signals pre-
sent on the VL side of the device appear as a higher-
voltage logic signal on the VCC side of the device, and
vice-versa. The MAX13013/MAX13014/MAX3023 bidi-
rectional level translators allow data translation in either
direction (VL
VCC) on any single data line. The
MAX13013/MAX13014/MAX3023 accept VL from +1.2V
to (VCC - 0.4V) and operate with VCC from +1.65V to
+3.6V, making them ideal for data transfer between
low-voltage ASICs/PLDs and higher voltage systems.
When in tri-state mode, the MAX13013/MAX13014/
MAX3023 reduce the VCC supply current to 0.03A,
and the VL supply current to 0.1A. These devices
operate at a guaranteed data rate of 100Mbps for VL >
1.8V.
Level Translation
For proper operation, ensure that +1.65V
≤ VCC ≤ +3.6V,
and +1.2V
≤ VL ≤ VCC - 0.4V. During power-up
sequencing, VL
≥ VCC does not damage the device.
During power-supply sequencing, when VCC is floating
and VL is powering up, up to 40mA current can be
sourced to each load on the VL side, without the device
latching up. The maximum data rate depends heavily on
the load capacitance (see the Typical Operating
Characteristics Rise/Fall Time graph), output impedance
of the driver, and the operating voltage range (Table 1).
Input Driver Requirements
The MAX13013/MAX13014/MAX3023 architecture is
based on a one-shot accelerator output stage (see
Figure 5). Accelerator output stages are in tri-state
mode except when there is a transition on any of the
translators on the input side, either I/O VL_ or I/O VCC_.
A short pulse is then generated during which the accel-
erator output stages become active and charge/dis-
charge the capacitances at the I/Os. Due to the
architecture, both sides become active during the one-
shot pulse. This can lead to some current feeding into
the external source that is driving the translator.
However, this behavior simply helps to speed up the
transition on the driven side.
For proper operation, the driver has to meet the follow-
ing conditions: less than 25
output impedance and
greater than 20mA peak output current capability.
Table 1. Data Rate
VL (V)
GUARANTEED DATA RATE (Mbps)
VL < 1.8
80
VL
≥ 1.8
100
P
ONE-SHOT
VCC
VL
I/O VL
I/O VCC
150
4k
I/O VCC_ TO I/O VL_ PATH
I/O VL_ TO I/O VCC_ PATH
N
ONE-SHOT
P
ONE-SHOT
N
ONE-SHOT
Figure 5. Simplified Functional Diagram (One I/O Line)
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