參數(shù)資料
型號(hào): MAX2463EAI
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類(lèi): 無(wú)繩電話/電話
英文描述: 900MHz Image-Reject Transceivers
中文描述: TELECOM, CELLULAR, RF AND BASEBAND CIRCUIT, PDSO28
封裝: 5.30 MM, MO-150, SSOP-28
文件頁(yè)數(shù): 8/14頁(yè)
文件大?。?/td> 250K
代理商: MAX2463EAI
M
900MHz Image-Reject Transceivers
8
_______________________________________________________________________________________
Pin Description
Supply Voltage Input for Receive Low-Noise Amplifier. Bypass with a 47pF low-inductance capacitor to
GND (pin 7 if possible).
Ground Connection for Receive Low-Noise Amplifier
Ground Connection for Signal-Path Blocks, except LNA
6
Receiver RF Input, single-ended. The input match shown in Figure 1 maintains an input VSWR of better
than 2:1 from 902MHz to 928MHz.
5
Transmit Gain-Control Input. Connect to V
CC
for highest gain and best temperature stability. When
driven with a control voltage, the IF buffer gain can be adjusted over a 36dB range (see
Typical
Operating Characteristics
).
4
V
CC
RXIN
TXGAIN
Prescaler/Oscillator Buffer Output. In divide-by-64/65 mode (DIV1 = low), the output level is 500mVp-p
into a high-impedance load. In divide-by-1 mode (DIV1 = high), this output delivers -8dBm into a 50
load. AC couple to this pin.
21
Transmit Bias Compensation Pin. Bypass with a 47pF low-inductance capacitor and 0.01μF to GND.
Do not make any other connections to this pin.
14
No Connect. Not internally connected.
13
Ground connection for the Prescaler. Tie PREGND to ground for normal operation. Leave floating to
disable the prescaler and the output buffer. Tie MOD and DIV1 to ground and leave PREOUT floating
when disabling the prescaler.
CAP2
N.C.
Transmitter IF Input, 330
, single-ended. AC couple to this pin.
12
Single-Ended, 330
IF Output. AC couple to this pin.
3
Receive Bias Compensation Pin. Bypass with a 47pF low-inductance capacitor and 0.01μF to GND.
Do not make any other connections to this pin.
2
Supply-Voltage Input for Master Bias Cell. Bypass with a 47pF low-inductance capacitor and 0.1μF to
GND (pin 28, if possible).
1
FUNCTION
PIN
Low-Noise Amplifier Gain-Control Input. Drive this pin high for maximum gain. When LNAGAIN is pulled
low, the LNA is capacitively bypassed and the supply current is reduced by 4.5mA. This pin can also be
driven with an analog voltage to adjust the LNA gain in intermediate states. Refer to the Receiver Gain
vs. LNAGAIN Voltage graph in the
Typical Operating Characteristics,
as well as Table 1.
10
PA Predriver Output. See Figure 1 for an example matching network, which provides better than 2:1
VSWR from 902MHz to 928MHz.
9
TXIN
LNAGAIN
TXOUT
7
8
GND
GND
RXOUT
CAP1
V
CC
NAME
Supply Voltage Input for Signal-Path Blocks, except LNA. Bypass with a 47pF low-inductance capacitor
and 0.01μF to GND (pin 8, if possible).
11
V
CC
20
PREOUT
PREGND
Modulus Control for the Divide-by-64/65 Prescaler: high = divide-by-64, low = divide-by-65. Note that
the DIV1 pin must be at logic low when using the prescaler mode.
19
Driving VCOON with a logic high turns on the VCO, phase shifters, VCO buffers, and prescaler. The
prescaler can be selectively disabled by floating the PREGND pin.
17
Driving RXON with a logic high enables the LNA, receive mixer, and IF output buffer. VCOON must also
be high.
16
MOD
VCOON
RXON
Driving TXON with a logic high enables the transmit IF variable-gain amplifier, upconverter mixer, and PA
predriver. VCOON must also be high.
15
TXON
Driving DIV1 with a logic high disables the divide-by-64/65 prescaler and connects the PREOUT pin
directly to an oscillator buffer amplifier, which outputs -8dBm into a 50
load. Tie DIV1 low for divide-by-
64/65 operation. Pull this pin low when in shutdown to minimize off current.
18
DIV1
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