參數(shù)資料
型號: MAX2369EGM+TD
廠商: Maxim Integrated
文件頁數(shù): 10/16頁
文件大?。?/td> 229K
描述: IC TRANSMITTER QUAD 48QFN-EP
標準包裝: 2,500
頻率: 120MHz ~ 235MHz
應用: 手機,GAIT 手持話機,LAN,PCS,TDMA,WAN,WLL
功率 - 輸出: 5.8dBm ~ 12dBm
電流 - 傳輸: 6.5mA ~ 155mA
數(shù)據(jù)接口: PCB,表面貼裝
天線連接器: PCB,表面貼裝
電源電壓: 2.7 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
封裝/外殼: 48-QFN 裸露焊盤
包裝: 帶卷 (TR)
Complete Dual-Band
Quadrature Transmitter
10   ______________________________________________________________________________________
The IFM register sets the main frequency divide ratio
for the IF PLL. The IFR register sets the reference fre-
quency divide ratio. The IF VCO frequency can be
determined by the following:
IF VCO frequency = f
REF

(IFM / IFR)
where f
REF
is the external reference frequency.
The operational control register (OPCTRL) controls the
state of the MAX2369. See Table 3 for the function of
each bit.
The configuration register (CONFIG) sets the configura-
tion for the IF PLL and the baseband I/Q input levels
See Table 4 for a description of each bit.
The test register is not needed for normal use.
Power Management
Bias control is distributed among several functional
sections and can be controlled to accommodate many
different power-down modes as shown in Table 5.
The shutdown control bit is of particular interest since it
differs from the SHDN pin. When the shutdown control
bit is active (SHDN_BIT = 0), the serial interface is left
active so that the part can be turned on with the serial
bus while all other functions remain shut off. In contrast,
Table 1. Register Power-Up Default States
Table 2. Register Initialization for F
REF
=
19.44MHz, F
IF
= 181.26MHz,
F
COMP
= 360kHz
Figure 1. Register Configuration
MSB
24 BIT REGISTER
LSB
DATA 20 BITS
ADDRESS 4 BITS
B19    B18    B17    B16    B15    B14    B13    B12    B11    B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
A3
A2
A1
A0
IFM DIVIDE RATIO REGISTER (14 BITS)
ADDRESS
X
X
X
X
X
X
B13    B12    B11    B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
0
0
1
0
IFR DIVIDE RATIO REGISTER (11 BITS)
ADDRESS
X
X
X
X
X
X
X
X
X
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
0
0
1
1
CONTROL REGISTER (16 BITS)
ADDRESS
X
X
X
X
B15    B14    B13    B12    B11    B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
0
1
0
0
CONFIGURATION REGISTER (16 BITS)
ADDRESS
X
X
X
X
B15    B14    B13    B12    B11    B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
0
1
0
1
TEST REGISTER (8 BITS)
ADDRESS
X
X
X
X
X
X
X
X
X
X
X
X
B7
B6
B5
B4
B3
B2
B1
B0
0
1
1
1
X = DONT CARE
REGISTER   DEFAULT   ADDRESS
FUNCTION
IFM
6519 dec
0010
b
IF M divider count
IFR
0492 dec
0011
b
IF R divider count
OPCTRL
892F hex
0100
b
Operational control
settings
CONFIG
D03F hex
0101
b
Configuration and
setup control
TEST
0000 hex
0111
b
Test-mode control
REGISTER   DEFAULT   ADDRESS
FUNCTION
IFM
1007 dec
0010
b
IF M divider count
IFR
0054 dec
0011
b
IF R divider count
OPCTRL
890F hex
0100
b
Operational control
settings
CONFIG
903D hex
0101
b
Configuration and
setup control
TEST
0000 hex
0111
b
Test-mode control
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