參數(shù)資料
型號(hào): MAX2079CXE+T
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 17/49頁(yè)
文件大?。?/td> 0K
描述: IC OCT ULTRASOUND RCVR 144CTBGA
標(biāo)準(zhǔn)包裝: 1,000
系列: *
Low-Power, High-Performance, Fully Integrated
Octal Ultrasound Receiver (Octal LNA, VGA,
AAF, ADC, and CWD Beamformer)
MAX2079
24
Maxim Integrated
Figure 2. CWD Output Beamforming Example
common mode is established internally to allow for
AC-coupling. The self-biased input common-mode volt-
age defaults to 1.2V. The differential clock signal can
also be DC-coupled if the externally established com-
mon-mode voltage is constrained to the specified clock
input common-mode range of 1V to 1.4V. A differential
input termination of 100I can be switched in by pro-
gramming the CLKIN Control register (04h[4], Table 19).
For single-ended operation, connect CLKIN- to GND
and drive the CLKIN+ input with a logic-level signal.
When the CLKIN- input is grounded (or pulled below the
threshold of the clock-mode detection comparator), the
differential-to-single-ended conversion stage is disabled
and the logic-level inverter path is activated. The input
common-mode self-bias is disconnected from CLKIN+,
and provides a weak pullup bias to AVDD for CLKIN-
during single-ended clock operation.
Figure 3. Digital Highpass Filter
CW_IOUT+
CW_IOUT-
CW_QOUT-
CW_QOUT+
+V
LO
DIVIDER
TO I CHANNEL
CWD ADC
TO Q CHANNEL
CWD ADC
CWD
I CHANNELS IN
CWD
Q CHANNELS IN
CWD
I/Q LO
(BYPASS)
HPF1
CONTROL BITS
R1
T
HPF1 [3:0]
T
(BYPASS)
HPF2
R2
T
HPF2 [3:0]
T
G1
ATTEN [1:0]
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